How Synopsys Interface IP and Arm Interoperate to Accelerate System IO and Memory Performance

This course will be held Online

In this webinar, Synopsys and Arm describe how their recent collaboration helps maximize system performance and shorten Arm-based SoC design cycles. Learn how to minimize HPC/data center SoC design risk and ensure end-to-end IP integration, using available Arm reference designs and interoperability reports. Find out how Synopsys’ interface IP for the most widely used protocols …

Analyzing Memory Bus to Meet with DDR Specifications

Online

Part of Simulating for High-Speed Digital Insights series April 14, 2022 | 10:00 AM PT / 1:00 PM ET Due to ever increasing data demand, the speed grade for memory is now in the multi-gigabit range. Memory bus design becomes a lot more complicated with tighter design margins due to higher crosstalk between vias and traces along …

Flash Memory Summit Conference

Santa Clara Convention Center 5001 Great America Pkwy, Santa Clara, CA, United States

Why Attend Flash Memory Summit? FMS is the best networking opportunity in the storage industry! The 2022 conference is expanding beyond flash memory to address all forms of high performance memory. Summit organizers welcome your submissions on a range of memory technologies including NAND Flash, DRAM, MRAM, ReRAM, and DNA storage. Submissions are also encouraged …

Learn How to Efficiently Achieve Accurate Experimental Etch Profiles in FinFET and Memory Applications with Victory TCAD Solution

Online

When: August 11, 2022 Where: Online Time: 10:00am-10:30am-(PDT) Language: English When employing process simulation to generate a complex device structure, TCAD engineers often face the task of reproducing the exact etch profile that has been observed in semiconductor fabrication. Silvaco Victory Process offers several geometric models to efficiently achieve etch geometries that accurately match microscopy …

Webinar: Protocol and Memory Interface Verification in the Shrinking World of 3DIC

Online

Summary Emerging 2.5D and 3DIC packaging technologies enable more design complexity, and bring some new verification challenges. We look at how to scale your verification capability to match and how to plan ahead for verification of die-to-die interconnect protocols such as UCIe and memory verification with HBM. Packaging technologies for 2.5D and 3DIC are becoming …

Creating Reliable Memory Interfaces Fast and Easy

This course will be held Online

Part of Keysight's 'Simulating for High-Speed Digital Insights' webinar series October 13, 2022 | 10:00 AM PT / 1:00 PM ET Successful memory interface design is more than building and simulating one design that works to the given specification. As a designer, your success relies on making a robust implementation that works for different corner cases, process variations, BOM …

Memory Technology Symposium

Online

Nov 29th, 2022 | 8:00 AM PST Nov 30th, 2022 | 8:00 AM GMT+8 Join this Virtual Event Advancements in memory technology are fueling rapid growth in big data applications across AI, 5G, Automotive, and HPC. These demanding applications create many challenges for memory designers. Some long-standing challenges are exacerbated, while the latest technology nodes …

The 25th Semiconductor Exhibition (SEDEX 2023)

Seoul, Korea Seoul, Korea, Republic of

Why SEDEX The Semiconductor Exhibition will be held at COEX from October 25 to 27, 2023. It is among one of the most outstanding exhibitions that covers the full spectrum of the semiconductor industry supply chain. No other event in the world showcases a full range of semiconductor products including SoC, IP, Memory, sensor, equipment/components …

Webinar: Pushing the Speed Envelope for Memory System Designs

Online

Time November 28, 2023 | 1:00 PM EST About Memory interface speeds keep increasing to meet performance demand. For instance, DDR5 is 275% faster than DDR4, reaching 8800 MT/s or more. Higher speeds also complicate memory design and validation. To achieve the next memory standard, designers need a connected workflow that streamlines time-to-insight from concept …