ccix

SoC designers, looking to get a jump start on their PCI Express (PCIe) 6.0 designs must be aware of several new considerations in addition to doubling of the data rate to 64 GT/s. Accessing a complete IP solution that offers optimized performance and seamless interoperability between the controller and PHY, achieving timing closure at 1+ …

Continue reading "PCI Express 6.0 Design Considerations and IP Implementation"