CadenceCONNECT: Jasper User Group 2025 is October 29 and 30 in San Jose, CA. This interactive, in-depth technical conference connects designers, verification engineers, and engineering managers from around the world …
As digital chip design complexity grows, engineering teams face increasing pressure to meet aggressive PPA targets on tight schedules. To overcome this challenge, the EDA industry requires a revolutionary shift towards AI. Siemens EDA is leading this transformation by implementing a comprehensive strategy that combines machine learning, reinforcement learning, generative, and agentic AI across the …
Description BLT, an AMD Premier Design Services Partner and Authorized Training Provider, presents this webinar. Unlock the potential of the AMD Kria SOM and discover Time-Sensitive Networking (TSN) benefits for your applications. In this session, you’ll explore the TSN-ROS application and its role in enhancing communications within a TSN framework. Join our hands-on demonstration to …
October 29, 2025 - 11:00 AM EST October 30, 2025 – 10:00 AM JST/KST Discover the 5 Critical Memory Market Trends Reshaping Semiconductors in 2026 AI workloads, HBM4 adoption, and …
Continue reading "Webinar: 5 Expectations for the Memory Market in 2026"
Semiconductor and integrated circuit developments continue to proceed at an incredible pace. The industry as a whole has gotten to this point of incredible complexity through the process of countless …
Strengthen your knowledge and skills by learning about new packaging technologies in Fan-in, Fan-out WLP, Embedded packaging technology, System on Chip (SOC), System in Package (SiP), 3D IC, WLP, TSV, …
Scaling Together in a Dynamic World The photonic chip industry is reaching new heights - but scaling production, applications, and investments requires a united effort. As demand surges for high-speed, …
Connect to the embedded community With its 20 years of history and experience in Europe, embedded world is the most professional and largest exhibition in its field, and has accumulated …
November 4, 2025 | 10:00 AM PST This webinar will present advanced simulation tools and techniques for the design of GaN power amplifiers with increased assurance of stable operation that goes beyond simple k-factor analysis. The methods will be demonstrated using Qorvo GaN technology and related non-linear models that have been modified to facilitate advanced …
Details Imaging radar has rapidly evolved into a critical technology for autonomous systems, with patent activity accelerating significantly over the past decade. From 2015 to 2024, global imaging radar patent publications increased more than tenfold, fueled by the rise of autonomous driving, 4D radar integration, AI-based perception, and sensor fusion. This surge has created an …
High-Level Synthesis (HLS) is design flow in which design intent is described at a higher level of abstraction such as SystemC/C++/Matlab/etc. HLS tools are expected to synthesize this code to RTL which can be input to the traditional RTL downstream flow (RTL/GDS). Formal check tools are difficult to be analyzed on generated RTL (as the …
Continue reading "Webinar: HLV – Formal Verification of Synthesizable C++/SystemC Designs"
Join us for this engaging Master Class with Benyamin Davaji, PhD, Assistant Professor of Electrical and Computer Engineering at Northeastern University and Peter Doerschuk, Professor of Electrical and Computer Engineering and Biomedical Engineering at Cornell University, as they explore the role of digital twin models in advancing semiconductor manufacturing. The masterclass will highlight how data-guided …
