Webinar: Mastering SoC Design and Verification for DO-254 Compliance – Balancing Complexity and Safety (hosted by ConsuNova)

This course will be held Online

Presenters: Martin Beeby, Head of Advanced Avionics Systems and Managing Director of ConsuNova EU and Janusz Kitel, DO-254 Program Manager at Aldec Inc. Abstract: System on Chip (SoC) devices are transforming …

SPIE Photonics West 2025

The Moscone Center The Moscone Center, San Jose, CA, United States

Browse the 2025 program; discover all the ways you'll connect with colleagues Join the world’s largest photonics technologies event. Learn the most cutting-edge research in biomedical optics, biophotonics, industrial lasers, …

DesignCon 2025

Santa Clara Convention Center 5001 Great America Pkwy, Santa Clara, CA, United States

The Must Attend Event for Chip, Board, and Systems Design Engineers DesignCon is the premier high-speed communications and system design conference and exposition, offering industry-critical engineering education in the heart …

DVClub Europe: Edinburgh

Edinburgh Futures Institute, The University of Edinburgh 1 Lauriston Pl, Edinburgh

Theme: Mixed Signal Verification Analog mixed signal chips continue to grow in both demand and complexity, and a consistent efficient verification approach remains a key topic for concern. This DVClub will …

Leti Photonics Workshop 2025

San Francisco Museum of Modern Art 151 3rd Street, San Francisco, CA, United States

Breakthroughs in photonics: network and innovate with leading experts and industrial players Why you should attend CEA-Leti leverages advances in semiconductors to enable far-reaching changes in photonic technologies. Join us …

2025 IEEE International Solid-State Circuits Conference (ISSCC)

San Francisco Marriott Marquis 780 Mission Street, San Francisco, CA, United States

About ISSCC The International Solid-State Circuits Conference is the foremost global forum for presentation of advances in solid-state circuits and systems-on-a-chip. The Conference offers a unique opportunity for engineers working at the cutting edge of IC design and application to maintain technical currency, and to network with leading experts. REGISTER HERE

SMTA Wafer-Level Packaging Symposium

Hyatt Regency San Francisco Airport 1333 Bayshore Highway, Burlingame, CA, United States

Thank you to those who attended and participated in the 2024 SMTA Wafer-Level Packaging Symposium! Their presence contributed to the success of this event, and we are truly thankful for their active engagement throughout the symposium! The WLPS showcased a rich and diverse technical program, featuring cutting-edge presentations and discussions on semiconductor and packaging technologies. …