ICCAD 2025

The 2025 International Conference on Computer-Aided Design Call For Papers Jointly sponsored by IEEE and ACM, IEEE ICCAD is the premier forum to explore new challenges, present leading-edge innovative solutions, …

CadenceCONNECT: Jasper User Group 2025

San Jose Convention Center 150 W San Carlos St, San Jose, CA, United States

CadenceCONNECT: Jasper User Group 2025 is October 29 and 30 in San Jose, CA. This interactive, in-depth technical conference connects designers, verification engineers, and engineering managers from around the world to share the latest design and verification practices based on Cadence’s Jasper formal verification technologies and methodologies. The Jasper User Group Conference is the premier …

SemIsrael Expo 2025

Connecting the Dots: Empowering the Semiconductor Community SemIsrael Expo 2025 is the premier professional semiconductor event in Israel. The event brings together hundreds of Israeli semiconductor professionals from all fields …

SC25

The International Conference for High Performance Computing, Networking, Storage, and Analysis HPC Ignites. St. Louis is the place to be this fall as the high performance computing community convenes for …

SEMICON Europa 2025

SEMICON Europa 2025 is co-located with productronica and will take place in November 18-21, 2025 in Munich, Germany. This year’s theme Global Collaborations for European Economic Resilience expresses that global collaborations are not …

CadenceTECHTALK: iPegasus Verification System for Virtuoso Studio

Online

Speaker: Hong-Cheang Quek, AE Director 10:00am~11:00am iPegasus Verification System for Virtuoso Studio 11:00am~11:15am Q&A Description: Today's complex SoC designs significantly increase layout creation and verification time, especially at advanced nodes. To meet overall demand for faster design cycle turnaround time, bridge a demand gap, and improve productivity between custom implementation and physical verification tools, Cadence …

CadenceTECHTALK: Quantus Insight: Intelligent Parasitic Debugging, Optimization, and Signoff Closure

Online

Speaker: Kee Tat Ong, Principal Application Engineer 10:00am~11:00am Quantus Insight: Intelligent Parasitic Debugging, Optimization, and Signoff Closure 11:00am~11:15am Q&A Description: With more designs migrating to advanced process nodes, chips are getting smaller, but design complexity is increasing in order to deliver better power, performance, or area. These optimizations are restricted by the time window to …

CES 2026

The world’s most powerful tech event is your place to experience the innovations transforming how we live. This is where global brands get business done, meet new partners and where …

2026 IEEE International Solid-State Circuits Conference (ISSCC)

San Francisco Marriott Marquis San Francisco Marriott Marquis, 780 Mission Street, San Francisco, CA, United States

About ISSCC The International Solid-State Circuits Conference is the foremost global forum for presentation of advances in solid-state circuits and systems-on-a-chip. The Conference offers a unique opportunity for engineers working …