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Description BLT, an AMD Premier Design Services Partner and Authorized Training Provider, presents this webinar. When it comes to embedded software development, managing multiple tools, maintaining version control, and navigating complex workflows can feel overwhelming. The AMD Vitis™ Unified IDE simplifies the process by integrating Vitis IDE, Vitis Analyzer, and Vitis HLS into a single, …
Failure and Yield Analysis is an increasingly difficult and complex process. Today, engineers are required to locate defects on complex integrated circuits. In many ways, this is akin to locating a needle in a haystack, where the needles get smaller and the haystack gets bigger every year. Engineers are required to understand a variety of …
San Jose McEnery Convention Center
San José McEnery Convention Center, 150 W San Carlos St, San Jose, CA, United States
Join us at WISH, GSA WLI’s premier technical conference that promises to be an inspiring celebration of innovation and empowerment. With around 1,000 attendees, including industry luminaries, visionary entrepreneurs, and brilliant university students in STEM, this event will showcase the evolving landscape of technology. Attendees can look forward to inspiring keynotes from trailblazers who are …
it-sa Expo&Congress in Nuremberg is Europe's largest trade fair for IT security... ...and one of the most important dialogue platforms for IT security solutions. The trade fair covers the entire range of products and services in the field of cybersecurity: hardware, software, training and consulting services as well as Security as a Service. Important topics …
Phoenix Convention Center
100 N 3rd St, Phoenix, AZ, United States
SEMICON West 2025 makes its debut in Phoenix, October 7–9—positioning the city as a key hub for innovation and industry growth. This milestone event gathers global leaders across the microelectronics supply chain to explore transformative technologies, develop the future workforce, and drive strategic collaboration. Now more than ever, we are STRONGER TOGETHER. Programs + Events -CEO …
Palau de Congressos
Palau de Congressos, Av. de la Reina Maria Cristina, s/n, Sants-Montjuïc, Barcelona, Spain
We're back in the vibrant city of Barcelona, bringing together experts from across the industry From 7th-9th October 2025, we’re reuniting the AutoSens community at the Palau de Congressos in Barcelona to shape the future of ADAS and AV. With over 60 expert speakers, engaging panels, technical case studies, and exploration of 12 key themes, …
San Jose Convention Center
150 W San Carlos St, San Jose, CA, United States
The OCP Summit is the premier event uniting the most forward-thinking minds in open IT Ecosystem development. The Summit presents a unique platform for our Community from around the globe to share their insights, foster partnerships and showcase cutting-edge advancements in open hardware and software. *Join us in San Jose October 13-16 for the 2025 OCP …
ABOUT PAINE Physical inspection of electronics has grown significantly over the past decade and is becoming a major focus for the chip designers, original equipment manufacturers, and system developers. The complex long life of the electronic devices coupled with their diverse applications is making them increasingly vulnerable to various forms of threats and inspection. Large …
The IEEE/ACM International Symposium on Microarchitecture® is the premier forum for presenting, discussing, and debating innovative microarchitecture ideas and techniques for advanced computing and communication systems. This symposium brings together researchers in fields related to microarchitecture, compilers, chips, and systems for technical exchange on traditional microarchitecture topics and emerging research areas. The MICRO community has enjoyed a …
Santa Clara Convention Center
Santa Clara Convention Center, 5001 Great America Pkwy, Santa Clara, CA, United States
RISC-V is defining the future of open computing by providing unprecedented freedom to innovate. More than 13 billion RISC-V cores have shipped, powering new innovations in AI/ML, wireless, automotive, data center, space, IoT, embedded and more. Each day, thousands of engineers around the world collaborate and contribute to advance RISC-V. The RISC-V community shares the …
Achieving Timing Closure in FPGA Designs Workshop Do you find it challenging to close timing in your FPGA design? This workshop will guide you through leveraging AMD Vivado’s tools, optimizing your design, and applying best practices for static timing analysis to achieve reliable timing closure. Gain hands-on experience with timing closure techniques and learn strategies to improve …
The 2025 International Conference on Computer-Aided Design Call For Papers Jointly sponsored by IEEE and ACM, IEEE ICCAD is the premier forum to explore new challenges, present leading-edge innovative solutions, and identify emerging technologies in the electronic design automation research areas. IEEE ICCAD covers the full range of CAD topics – from device and circuit …
San Jose Convention Center
150 W San Carlos St, San Jose, CA, United States
CadenceCONNECT: Jasper User Group 2025 is October 29 and 30 in San Jose, CA. This interactive, in-depth technical conference connects designers, verification engineers, and engineering managers from around the world to share the latest design and verification practices based on Cadence’s Jasper formal verification technologies and methodologies. The Jasper User Group Conference is the premier …
Description BLT, an AMD Premier Design Services Partner and Authorized Training Provider, presents this webinar. Unlock the potential of the AMD Kria SOM and discover Time-Sensitive Networking (TSN) benefits for your applications. In this session, you’ll explore the TSN-ROS application and its role in enhancing communications within a TSN framework. Join our hands-on demonstration to …
Semiconductor and integrated circuit developments continue to proceed at an incredible pace. The industry as a whole has gotten to this point of incredible complexity through the process of countless breakthroughs and developments in wafer fab processing. Today's wafer fab contains some of the most complex and intricate procedures ever developed by mankind. Wafer Fab Processing is …
Fraunhofer Institute for Reliability and Microintegration IZM
Gustav-Meyer-Allee 25, Building 17/3, Berlin, Germany
On 6 and 7 November, Fraunhofer IZM is inviting customers and partners from industry to Berlin for its “Electronic Packaging Days”. The event is designed to facilitate direct exchange between IZM researchers and companies. The aim is to present current research work and technological developments in the field of microelectronic packaging and heterogeneous system integration …
As the global semiconductor landscape continues to evolve, Vietnam is positioning itself for a promising future in the semiconductor industry. SEMIEXPO Vietnam will be a pivotal event, exploring opportunities for businesses across the semiconductor value chain, from assembly and testing, to fabless/design. This premier event will highlight how local players can elevate Vietnam’s position in …
Connecting the Dots: Empowering the Semiconductor Community SemIsrael Expo 2025 is the premier professional semiconductor event in Israel. The event brings together hundreds of Israeli semiconductor professionals from all fields and aspects of the semiconductor industry. The Expo will host some 750 semiconductor professionals from all the Israeli semiconductor community; local fabless & startups, local …
America’s Center
America’s Center, 701 Convention Plaza, St. Louis, MO, United States
The International Conference for High Performance Computing, Networking, Storage, and Analysis HPC Ignites. St. Louis is the place to be this fall as the high performance computing community convenes for an exhilarating week of sessions, speakers, and networking at its finest. SC is an unparalleled mix of thousands of scientists, engineers, researchers, educators, programmers, and …
Amsterdam Marriott Hotel
Stadhouderskade 12, Amsterdam, Netherlands
The Netherlands has been the home for Hardwear.io since 2015. We are very excited to host the industry from automotive, healthcare, semiconductor, IoT, industrial control systems and Govt/Defences Institutes to join us for Hardwear.io NL scheduled on 17th Nov to 21st Nov 2025 at Amsterdam Marriott Hotel Learn, share, build, collaborate with 100+ companies attending …
SEMICON Europa 2025 is co-located with productronica and will take place in November 18-21, 2025 in Munich, Germany. This year’s theme Global Collaborations for European Economic Resilience expresses that global collaborations are not just beneficial for Europe's resilience, they are essential. In today's interconnected world, Europe cannot afford to operate in isolation. By working closely with other nations, …
ICM – International Congress Center Messe München
Messe München GmbH, Messegelände, München, Germany
Discover how the latest MEMS and imaging technologies are enabling next-level value creation across industries. Explore cutting-edge AI-enhanced sensing, data fusion, and their transformative impact on automotive, healthcare, and smart systems. Learn how these technologies are driving Europe's leadership in the sensor revolution while shaping a more intelligent, interconnected future. Join us in Sensing (R)evolution: …
From Theory to Practice: Applying Timing Constraints Workshop Do you struggle to identify which constraints are needed for a design or how to properly input them? This workshop will cover how to use features in Vivado, clock domain crossing strategies, and how to get the most out of static timing analysis for Versal devices. This …
Signia by Hilton San Jose
170 S Market St, San Jose, CA, United States
Date: Nov. 20, 2025 Time: SIA Reception at 5:00 pm Dinner, Awards Presentations, & Keynote Remarks at 6:30 pm After-Dinner Reception at 8:30 pm Location: Signia by Hilton San Jose 170 S Market St San Jose, Calif.95113 PRIORITY SPONSORSHIP PERIOD NOW OPEN! The 2025 SIA Awards Dinner Priority Sponsorship Period is now open! Only Gold …
Description Clock domain crossings (CDCs) are a critical aspect of FPGA and embedded system design, and handling them correctly is essential for reliable operation. In this one-hour webinar, we’ll break down CDC fundamentals, explore best practices for managing single-bit and bus CDCs, and demonstrate how to leverage Xilinx Parameterized Macros (XPM) for seamless synchronization. Join …
100 YEARS of FETs: SHAPING the FUTURE of DEVICE INNOVATIONS Inside IEEE IEDM 2025 Focus Sessions Focus Session #1 - Efficient AI Solutions: Architecture, Circuit, and 3D Integration Innovations for Memory and Logic Focus Session #2 - Beyond Silicon: The Invisible Revolution in Thin-Film Transistors Focus Session #3 - From P-bits to Qubits: Classical, Quantum-Inspired …
Essential Debugging Techniques Workshop This workshop is for hardware engineers, system architects, and anyone who wants to learn best practices for debugging challenging issues encountered while developing FPGAs, SoCs, PCBs, and embedded systems using the Vivado Design Suite. The features and capabilities of the Vivado Integrated Logic Analyzer are covered in lectures and demonstrations, along with …
