"This period of pandemic and confinement has fostered telework and remote relationships. As a result, data transfers around the world have increased dramatically. During its annual Devices Workshop, CEA-Leti will share its vision on the management of data in all its forms, from capture to safe restitution. Join CEA-Leti in virtual mode for a remote discussion …
Theme: Cut Costs, Save Time, Reduce Risk Description: Choose sessions from experts around the globe — who will share their insights on how to improve the plan, create, and verify phases of …
Profiling software on remote systems can be difficult. Discover how the Intel® VTune™ Profiler Server can simplify profiling of HPC clusters over low-bandwidth connections, making it easier to collect, analyze …
Continue reading "Easier Profiling of Cloud, Cluster and Embedded Systems using a Profiling Server"
About ISSCC The International Solid-State Circuits Conference is the foremost global forum for presentation of advances in solid-state circuits and systems-on-a-chip. The Conference offers a unique opportunity for engineers working …
Continue reading "2021 International Solid-State Circuits Virtual Conference"
If you want to improve your MPI application performance, this webinar is for you. Find out how a cross-architecture, multi-fabric, message-passing library can help your apps perform better on HPC …
Continue reading "Be a Cluster Champion! Tune Your Way to MPI Performance"
February 23-February 25, 2021 Join the CEVA team to experience the smart sensing and wireless connectivity technologies that will shape our future. Visit us for a connected, interactive, and fully …
Produce Secure, High-quality Code Discover how you can easily produce secure, high-quality code with Klocwork. Klocwork is a static code analysis tool. It checks your code against coding rules. You …
Continue reading "Webinar: Klocwork Ensures the Security, Reliability, and Quality of Your Code"
System-in-package (SiP) designs for high-performance computing (HPC), high-speed networking, and AI applications are extremely complex. To achieve maximum performance without exceeding tight thermal and power constraints, these chips must be …
Continue reading "Electrothermal Signoff for 2.5D and 3D-IC Systems"
Traditional FPGA programming models and hardware description languages are not intuitive to many software developers. And even if they are, using them for iterative algorithm development is time consuming. This …
Join us: BLT is co-organizing this free, live online training event with Xilinx Customer Training and other Xilinx Authorized Training Providers. The two day event includes live instruction, optional labs, …
Continue reading "Getting Started with Xilinx Versal ACAP Platform"
Overview: Join this webinar to learn how Visual Design Diff helps analog/mixed-signal designers using the Cadence Virtuoso platform to manage ECO’s & conduct design reviews more efficiently. VDD gives design …
Continue reading "For Cadence Virtuoso Users : Manage ECOs and Design Reviews Efficiently"
Increase your machine learning model accuracy and performance with Intel-optimized XGBoost algorithms found in the Intel® AI Analytics Toolkit. Read More Gradient boosting has many real-world applications as a general-purpose …
Continue reading "Maximize Your CPU Resources for XGBoost* Training and Inference"
Join BittWare and Intel as we look at oneAPI™ with a focus on FPGAs. We will look at a real-world 2D FFT acceleration example which utilizes the Intel® Stratix® 10 MX including HBM2 memory …
Continue reading "Using Intel® oneAPI™ to Achieve High-Performance Compute Acceleration with FPGAs"
