OPENEDGES Technology at the 2024 Design Automation Conference

A leading memory subsystem IP provider, OPENEDGES Technology  (OPENEDGES) is set to unveil the 2.0 release of PHY Vision at the Design Automation Conference (DAC) 2024. The event will take place at the Moscone Center West, San Francisco, from June 24^th to 26^th, where attendees can experience firsthand the enhanced capabilities of this advanced LPDDR PHY visualization and exploration software.

PHY Vision 2.0 is a Graphical User Interface (GUI) software that allows users to configure, control, and visualize the behavior of OPENEDGES’ LPDDR PHY IPs in different operating conditions and applying analog tuning settings. Since its initial debut at last year’s DAC, PHY Vision has been upgraded with improvements in architecture, performance, and portability. The live demonstration will feature OPENEDGES’ 7nm LPDDR5X combo PHY IP and test platform, operating at a data rate of 8533 Mbps.

At OPENEDGES’ booth 2432, visitors can view a live demo of PHY Vision 2.0 and explore the many features and benefits of OPENEDGES’ LPDDR PHY IP, which include:

• Advanced protocol availability for mature technology nodes
• Cross-verification with OPENEDGES’ ORBIT Memory Controller (OMC)
• Reduced silicon footprint and area requirements
• Accelerated training time with support for firmware customization
• Fast frequency set point (FSP) switching
• Optimized low power states
• Simplified integration of HARD and SOFT IP and more.

Visitors to the Moscone Center West can also learn more about OPENEDGES’ most recent PHY achievement, the successful silicon bring-up of its LPDDR5X PHY IP on 5nm process technology.

OPENEDGES’ wholly owned subsidiary, The Six Semiconductor (TSS), which specializes in developing high-speed DDR PHY IP, will also be present at the booth. TSS engineers will engage with visitors to share their insights and expertise in memory sub-system planning and implementation for low-power systems.

OPENEDGES is a total memory subsystem IP provider offering DDR memory controller, DDR PHY, On-chip Interconnect, and NPU IPs, compatible with the latest DDR technology trends. Contact OPENEDGES here to schedule a meeting at booth #2432.

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