Webinar: Static Verification of RTL DFT Connectivity – Getting it Right the First Time!
Featured Speakers:
- Kiran Vittal, Synopsys
- Ayush Goyal, Synopsys
As System-on-Chip (SoC) designs become increasingly complex, ensuring reliable Design-for-Test (DFT) connectivity at the RTL stage is more important than ever. This Synopsys webinar will demonstrate how static verification techniques, powered by TestMAX™ Advisor on the VC SpyGlass® platform, can help you address connectivity challenges efficiently and accurately. Learn how robust connectivity checks can improve design quality and streamline your verification process.
Why You Should Attend:
- Discover best practices for verifying RTL DFT connectivity in modern SoC designs.
- See practical demonstrations of customizable connectivity checks and advanced GUI analysis tools.
- Learn how to detect both DFT and functional connectivity issues early in the design cycle.
- Gain insights from Synopsys experts on leveraging static verification for faster, more reliable design closure.
Don’t miss this opportunity to enhance your verification workflow—secure your spot today!
Featured Speakers
Executive Director, Synopsys
Kiran Vittal is the executive director of product management for the Synopsys Design-for-Test line of business in the Product Management and Markets Group. He has 25+ years of experience in EDA and semiconductor design.
Ayush Goyal
Senior Staff R&D Engineer, Synopsys
Ayush Goyal is Senior Staff R&D Engineer in the Hardware Analytics and Test Group at Synopsys. He joined Synopsys in 2016. He has been working in the EDA industry for the last 9 years focused in the areas of software-driven automation technologies.
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