Webinar: Shift-Left Compute Subsystem RTL Sign-Off with Software Aware VIP

Wednesday, March 11 – 8:00 AM Pacific

Design and verification teams consistently tell us that compute subsystems require software bring up much earlier than ever before. They need UEFI and Linux to run in simulation, they need protocol accuracy from day one, and they need a predictable path to signoff while integration risks rise every quarter. This struggle has become a shared industry reality. 

In this session we present a scalable methodology to accelerate the development and verification of Compute Subsystems such as Arm® Neoverse™ V3 Compute Subsystem (CSS)-based designs, with a shift-left in simulation and signoff using Avery Protocol VIP, CSS VIP, Software Aware VIP, Arm Fast Models and QEMU models.

This methodology helps teams reduce integration risks, shorten turnaround time, and gain system level confidence long before moving to emulation or prototypes. If you are a design or verification engineer, a firmware engineer or if you manage a team building next generation compute platforms, this is an event that will strengthen your technical path forward.

What You Will Learn: 

• Software Aware Verification IP and applications.
• Block level / Subsystem Compliance Testing with Software Aware VIP.
• Full CSS HW/FW/SW bring up and UEFI Bootup.
• Advanced debug of Hardware/Firmware/Software.

Who Should Attend:

• Verification Managers and Directors.
• Design and Verification Engineers.
• Firmware/Software Engineers.

Products Covered:

• Avery Verification IP.
• Software Aware VIP.
• System VIP (CSS).

Speakers:

Luis E. Rodriguez

Technical Product Manager, Siemens EDA

Luis E. Rodriguez is a Technical Product Manager at Siemens EDA.

Luis has 17+ years of experience in SoC and IP functional verification, specializing in developing market‑leading Verification IP.

He has contributed to protocol workgroups including PCIe, CCIX, Gen‑Z, and CXL, where he helped define CXL 2.0 compliance testing.

At Siemens, he focuses on partnerships and solutions for Software‑Aware VIP and supports cross‑functional integration of Verification IP with Siemens EDA tools and emerging Agentic AI.

He holds his master’s degree in computer science from National Taiwan University.

Amit Tanwar

Software Architect, Siemens EDA

Amit Tanwar is a Software Architect at Siemens EDA.

Amit has 18 years of experience in PCI Express and UVM/SystemVerilog‑based Verification IP development.

He specializes in building high‑performance, scalable, and software‑aware VIP solutions, and has contributed to multiple generations of advanced verification architectures across the semiconductor industry.

REGISTER HERE