From Theory to Practice: Applying Timing Constraints Workshop

From Theory to Practice: Applying Timing Constraints Workshop

Do you struggle to identify which constraints are needed for a design or how to properly input them? This workshop will cover how to use features in Vivado, clock domain crossing strategies, and how to get the most out of static timing analysis for Versal devices.

This workshop provides experience with understanding timing constraints for adaptive SoCs and strategies to improve design performance.

Gain experience with:

• Applying basic timing constraints
• Understanding virtual clocks
• Performing timing analysis
• Applying timing exception constraints
• Reviewing timing reports

This course focuses on the Versal architecture.

COST:

AMD is sponsoring this workshop, with no cost to students. Limited seats available.

REGISTER HERE