DVCon Japan 2025

The Design & Verification Conference & Exhibition is the premier conference on the application of languages, tools, methodologies and standards for the design and verification of electronic systems and integrated circuits. The conference is comprised of highly technical content, focusing on the practical aspects of design and verification techniques and their application in cutting edge projects. The hope is that attendees will learn from and adopt similar techniques to help improve their own design and verification flows, ultimately raising the state of the art across the industry.

DVCon Japan 2025 will be held in Shinagawa on August 20, 2025.

DVCon (Design and Verification Conference) is a conference sponsored by Accellera Systems Initiative. It focuses on solving problems in a wide range of fields, including logic design and architecture considerations for semiconductors and systems, functional verification, HW/SW co-verification, analog simulation, functional safety compliance and security verification, and application of AI development flows. This conference is for learning and discussing best practices in the application of languages, formats, methodologies, etc. of IEEE and Accellera standards.

DVCon has a history of over 30 years in the United States, and will be held in Japan from 2022. In 2022, the event was held online and on-demand, but in 2023 and 2024, it will be held in person. We were able to deliver a wide variety of in-depth content through various paper presentations, tutorial sessions, and exhibits by sponsors and exhibitors. We would like to express our gratitude to the audience, presenters, sponsors, and all those involved.

DVCon Japan 2025 will be held at a venue that is accessible by a 3-minute walk from the Takanawa Exit of Shinagawa Station. The morning will consist of general sessions and panel discussions, and the afternoon will consist of technical sessions, including many paper presentations and tutorials. At the same time, there will be exhibitions by sponsors, exhibitors, and associations. DVCon is a place to share and discuss the latest information in a wide range of fields, including functional verification strategies, SystemVerilog, UVM, UPF, SystemC, PSS, formal verification methodologies, HLS, AMS, and IP-XACT. It is also a place to deepen interactions between participants, presenters and participants, sponsors, and Accellera representatives.

We hope that designers, engineers, and managers will actively participate in the event. We look forward to seeing you all at the venue. Finally, we would like to take this opportunity to express our sincere gratitude to the sponsors who are supporting the event, as well as the Information Processing Society of Japan, the IEEE CEDA AJJC, and the Institute of Electronics, Information and Communication Engineers.

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