CadenceTECHTALK: Quantus Insight: Intelligent Parasitic Debugging, Optimization, and Signoff Closure

Speaker: Kee Tat Ong, Principal Application Engineer

10:00am~11:00am Quantus Insight: Intelligent Parasitic Debugging, Optimization, and Signoff Closure

11:00am~11:15am Q&A

Description: With more designs migrating to advanced process nodes, chips are getting smaller, but design complexity is increasing in order to deliver better power, performance, or area. These optimizations are restricted by the time window to tape out the design which has not increased proportionately. This means there is reduced time to debug and optimize the circuit. Quantus Insight is a tool to quickly analyze a circuit and obtain insights of the parasitic resistances and capacitances affecting the design and a mechanism to do rapid experimentation on an extracted design. For the front-end designer, Quantus insight allows the designer to gain a better understanding of the source of parasitic and to perform a what-if analysis on the design. For back-end layout engineers, Quantus Insight allows them to visualize the parasitic devices so that they can modify the layouts to meet the design constraints set by circuit designers

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