AI-Driven DRC Productivity Optimization: Revolutionizing Semiconductor Design

The semiconductor industry is undergoing a transformative shift with the integration of AI into DRC workflows, as showcased in the Siemens EDA presentation at the 2025 TSMC OIP. Titled “AI-Driven DRC Productivity Optimization,” this initiative, led by Siemens EDA’s David Abercrombie alongside AMD’s Stafford Yu and GuoQin Low, highlights a collaborative effort to enhance productivity and efficiency in chip design. The presentation outlines a comprehensive AI system that revolutionizes the entire EDA workflow, from knowledge sharing to automated fixing and debugging.

At the core of this innovation is the Siemens EDA AI System, which leverages a GenAI interface, knowledge base, and data lake to integrate AI tools across the portfolio. This system, deployable on customer hardware or cloud environments, supports a unified installation process and offers flexibility to incorporate customer data and models. Tools like the AI Docs Assistant and Calibre RVE Check Assist boost user understanding by providing instant answers and leveraging TSMC design rule data, respectively. The AI Docs Assistant, accessible via browser or integrated GUIs, uses retrieval-augmented generation to deliver relevant citations, while Calibre RVE Check Assist enhances debugging with specialized images and descriptions from TSMC.

Collaboration is a key pillar, with features like Calibre RVE Check Assist User Notes enabling in-house knowledge sharing. Designers can capture fixing suggestions and images, creating a shared knowledge base that enhances DRC-fixing flows across organizations. Meanwhile, Calibre DesignEnhancer automates the resolution of DRC violations on post-routed designs, using analysis-based modifications to insert sign-off DRC-clean interconnects and vias. This tool’s ability to handle complex rules and dependencies makes it a standalone DRC fixing solution.

Calibre Vision AI addresses the unique challenges of full-chip integration by offering AI-guided DRC analysis. It provides lightning-fast navigation through billions of errors, intelligent debug clustering, and cross-user collaboration tools like bookmarks and HTML reports. AMD’s testimonial underscores a 2X productivity boost in systematic error debugging, with Vision AI reducing OASIS database sizes and load times significantly. Signals analysis, such as identifying fill overlaps with clock cells or CM0 issues in breaker cells, accelerates root-cause identification.

This AI-driven approach, bolstered by AMD and TSMC collaborations, optimizes DRC sign-off productivity by boosting workflows, understanding, fixing, debugging, and collaboration. As the industry moves toward more complex designs, Siemens EDA’s AI system sets a new standard, promising faster cycle times and enhanced design robustness, paving the way for future innovations in semiconductor technology.

For more information contact Siemens EDA

Great presentation, absolutely.

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