Mentor Snags Two Awards at DesignCon

Oh, awards season! The glitz! The glamour! The most important and innovative new design products!

That last part is a key feature of the annual DesignVision awards and the Best in Test awards presented at DesignCon 2013. Mentor Graphics’ test products scored two wins: a DesignVision award for their new Tessent IJTAG product, and a Best in Test award for cell-aware (aka cell-internal) testing. While electronics industry awards may not offer the highest fashion, they do tell you what’s hot, and that’s often worth knowing.

Tessent IJTAG was recognized for enabling the new standard for the access and control of embedded IP, IEEE P1687, or IJTAG to its friends.

Some short overviews of the IJTAG standard are hereand here. Basically, IJTAG can create plug-n-play networks for IP, replacing ad-hoc and proprietary IP interfaces with a standardized interface. Mentor’s IJTAG software provides automation for the standard, so you can easily integrate any IEEE P1687-compliant IP into your design. This is a big deal, and translates into direct time and money savings from reduced test time and smaller tester memory requirements.

The Tessent IJTAG tool reads P1687 files and validates that the components are properly connected to the top-level access point. It then retargets IP-level procedural descriptions to the top-level and translates the results into Verilog test bench language and standard test vector formats like WGL, STIL or SVF. For a more detailed description of IJTAG and Mentor’s Tessent IJTAG, check out this Mentor whitepaper.

If that weren’t exciting enough, Mentor also won a Best in Test award for Tessent TestKompress with Cell-Aware ATPG. Cell-aware is a method by which the cell internals are characterized and modeled so ATPG can find defects that occur within the standard cells. Traditional fault models are abstractions of expected defect behavior and mostly target faults at the cell boundary. But with recent fabrication technologies, more than half of defects can occur within cells, which requires new cell-aware fault models that are based on analysis of the impact of defects within cell layouts.

The Mentor software automates the cell library characterization and offers a modeling syntax, UDFM (user-defined fault model). The cell internal fault models are automatically incorporated into TestKompress pattern generation using UDFM. In fact, you can use the UDFM capability to define any proprietary fault model you want, thus boosting the test quality for your specific process or application.

The cell-aware methodology Mentor devised ensures extremely high quality test patterns because it uses the physical characterization of cells to generate test pattern deterministically for potential defect locations. Mentor published some high-volume production test results with AMD proving that cell-aware testing significantly improves defect coverage and as such reduces defect rates of delivered IC significantly. You can download a paper they did with AMD at the last International Test Conference here (registration needed). The Mentor whitepaper on UDFM and the cell-aware methodology is here.