WP_Term Object
(
    [term_id] => 14
    [name] => Synopsys
    [slug] => synopsys
    [term_group] => 0
    [term_taxonomy_id] => 14
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 773
    [filter] => raw
    [cat_ID] => 14
    [category_count] => 773
    [category_description] => 
    [cat_name] => Synopsys
    [category_nicename] => synopsys
    [category_parent] => 157
    [is_post] => 
)
            
800x100 v4a (2)
WP_Term Object
(
    [term_id] => 14
    [name] => Synopsys
    [slug] => synopsys
    [term_group] => 0
    [term_taxonomy_id] => 14
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 773
    [filter] => raw
    [cat_ID] => 14
    [category_count] => 773
    [category_description] => 
    [cat_name] => Synopsys
    [category_nicename] => synopsys
    [category_parent] => 157
    [is_post] => 
)

Designing the Future: AI-Driven Multi-Die Innovation in the Era of Agentic Engineering

Designing the Future: AI-Driven Multi-Die Innovation in the Era of Agentic Engineering
by Daniel Nenni on 02-25-2026 at 8:00 am

1 abhijeet chakraborty chiplet summit keynote 2026

At the 2026 Chiplet Summit, Synopsys presented a bold vision for the future of semiconductor innovation: AI-driven multi-die design powered by agentic intelligence. As the semiconductor industry shifts rapidly toward chiplet-based architectures and 3D stacking, the complexity of design, verification, and system integration… Read More


Hardware is the Center of the Universe (Again)

Hardware is the Center of the Universe (Again)
by Lauro Rizzatti on 02-23-2026 at 10:00 am

Hardware is the Center of the Universe (Again) Figure 1

The 40-Year Evolution of Hardware-Assisted Verification — From In-Circuit Emulation to AI-Era Full-Stack Validation

For more than a decade, Hardware-Assisted Verification platforms have been the centerpiece of the verification toolbox. Today, no serious semiconductor program reaches tapeout without emulation or FPGA-prototyping… Read More


Smarter IC Layout Parasitic Analysis

Smarter IC Layout Parasitic Analysis
by Daniel Payne on 02-18-2026 at 10:00 am

ParagonX flow

IC layout parasitics dominate the performance of custom digital, analog and mixed-signal designs, so the challenge becomes how to identify the root causes and to quantify the effects of parasitics during early design stages. The old method of iterating between layout, extraction, SPICE simulation, followed by manual debug… Read More


Accelerating Static ESD Simulation for Full-Chip and Multi-Die Designs with Synopsys PathFinder-SC

Accelerating Static ESD Simulation for Full-Chip and Multi-Die Designs with Synopsys PathFinder-SC
by Kalar Rajendiran on 02-17-2026 at 10:00 am

SNPS PathFinder SC ESD Verification

As analog and mixed-signal designs become increasingly complex, parasitic effects dominate both design time and cost, consuming 30–50% of engineers’ effort in debugging and reanalyzing circuits. Addressing these multiphysics effects requires early verification strategies and reliable simulation solutions. Modern … Read More


Podcast EP330: An Overview of DVCon U.S. 2026 with Xiaolin Chen

Podcast EP330: An Overview of DVCon U.S. 2026 with Xiaolin Chen
by Daniel Nenni on 02-06-2026 at 10:00 am

Daniel is joined by Xiaolin Chen, Senior Director of Technical Product Management for Formal Solutions at Synopsys. She has over 20 years of experience applying formal technology in verification and partnering with customers to identify opportunities where formal methods are best suited to solve complex verification challenges.… Read More


2026 Outlook with Abhijeet Chakraborty VP, R&D Engineering at Synopsys

2026 Outlook with Abhijeet Chakraborty VP, R&D Engineering at Synopsys
by Daniel Nenni on 02-04-2026 at 10:00 am

Abhijeet Headshot

Tell us a little bit about yourself and your company.

My name’s Abhijeet Chakraborty and I’m Vice President of Engineering at Synopsys. I led the development of Synopsys Design Compiler-NXT, the industry’s leading synthesis product, and now oversee the company’s multi-die and 3DIC product portfolio. Throughout my career,… Read More


How 25G Ethernet, PCIe 5.0, and Multi-Protocol PHYs Enable Scalable Edge Intelligence

How 25G Ethernet, PCIe 5.0, and Multi-Protocol PHYs Enable Scalable Edge Intelligence
by Kalar Rajendiran on 02-03-2026 at 6:00 am

Ethernet Links Enabling In Vehicle Network and ADAS

Physical AI is changing how intelligent systems interact with the real world. These systems must sense, process, and respond to data in real time. Unlike cloud AI, Physical AI depends on fast local processing and reliable distributed communication. This shift creates a new challenge. Systems must move large volumes of sensor… Read More


Advances in ATPG from Synopsys

Advances in ATPG from Synopsys
by Daniel Payne on 02-02-2026 at 10:00 am

Synopsys TestMAX family

I first learned about ATPG – Automatic Test Program Generation in the 1980s at Silicon Compilers, then continued in the 90s at Viewlogic with the Sunrise tools, so it was illuminating to get an update from Synopsys on their ATPG technology by attending a webinar. Synopsys over the years has developed a family of test tools, shown … Read More


Synopsys and AMD Honored for Generative and Agentic AI Vision, Leadership, and Impact

Synopsys and AMD Honored for Generative and Agentic AI Vision, Leadership, and Impact
by Daniel Nenni on 01-29-2026 at 12:00 pm

Synopsys AMD Agentic AI Honor

Synopsys and AMD were recently selected by the World Economic Forum for inclusion in the WEF’s MINDS (Meaningful, Intelligent, Novel, Deployable Solutions) AI program, recognizing their leadership and real-world impact in applying generative and agentic AI to semiconductor design and engineering. This distinction places… Read More


Synopsys’ Secure Storage Solution for OTP IP

Synopsys’ Secure Storage Solution for OTP IP
by Kalar Rajendiran on 01-28-2026 at 6:00 am

Synopsys Secure Storage Solution for OTP IP

For decades, One-Time Programmable (OTP) memory has been viewed as a foundational element of hardware security. Because OTP can be written only once and cannot be modified afterward, it has traditionally been trusted to store cryptographic keys, secure boot code, device identity, and configuration data. Permanence was often… Read More