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Daniel is joined by Xiaolin Chen, Senior Director of Technical Product Management for Formal Solutions at Synopsys. She has over 20 years of experience applying formal technology in verification and partnering with customers to identify opportunities where formal methods are best suited to solve complex verification challenges.… Read More
Tell us a little bit about yourself and your company.
My name’s Abhijeet Chakraborty and I’m Vice President of Engineering at Synopsys. I led the development of Synopsys Design Compiler-NXT, the industry’s leading synthesis product, and now oversee the company’s multi-die and 3DIC product portfolio. Throughout my career,… Read More
I first learned about ATPG – Automatic Test Program Generation in the 1980s at Silicon Compilers, then continued in the 90s at Viewlogic with the Sunrise tools, so it was illuminating to get an update from Synopsys on their ATPG technology by attending a webinar. Synopsys over the years has developed a family of test tools, shown … Read More
Synopsys and AMD were recently selected by the World Economic Forum for inclusion in the WEF’s MINDS (Meaningful, Intelligent, Novel, Deployable Solutions) AI program, recognizing their leadership and real-world impact in applying generative and agentic AI to semiconductor design and engineering. This distinction places… Read More
For decades, One-Time Programmable (OTP) memory has been viewed as a foundational element of hardware security. Because OTP can be written only once and cannot be modified afterward, it has traditionally been trusted to store cryptographic keys, secure boot code, device identity, and configuration data. Permanence was often… Read More
Power has become a very hot (ha-ha) topic. The media has latched onto the emergence of massive AI datacenters disrupting energy pricing for consumers. Both as consumers and in industry we welcome faster and better features in our hand-held computing devices, cars, homes, industrial processes and businesses. But without further… Read More
The rapid evolution of RISC-V processors has introduced unprecedented verification challenges. Modern high-end RISC-V cores now incorporate complex features such as vector and hypervisor extensions, virtual memory systems, multi-level caches, advanced interrupt architectures, and multi-hart out-of-order execution.… Read More
Socionext’s recent run of rapid 3D-IC tape-outs is a noteworthy milestone for the industry with two successful tape-outs in just seven months for complex, multi-die designs aimed at AI and HPC workloads. That pace of iteration highlights how advanced packaging, richer EDA toolchains, and closer foundry-ecosystem collaboration… Read More
Cisco’s relentless push toward higher-performance networking silicon has placed extraordinary demands on its ASIC design methodology. As transistor densities continue to rise across advanced SoCs, traditional design-time guardbands are no longer sufficient to ensure long-term reliability, consistent performance,
Our good friend Scotten Jones wrote a paper on a product that has been in joint development with Synopsys and is now available. Scott is currently President Semiconductor Manufacturing Economics and Senior Fellow at TechInsights. Scott and I have discussed this product many times and I feel it is ground breaking technology for… Read More
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