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Podcast EP337: The Importance of Network Communications to Enable AI Workloads with Abhinav Kothiata

Podcast EP337: The Importance of Network Communications to Enable AI Workloads with Abhinav Kothiata
by Daniel Nenni on 03-27-2026 at 10:00 am

Daniel is joined by Abhinav Kothiata, a principal product manager for the Synopsys Ethernet IP portfolio. He has over 12 years of experience across engineering and product management, spanning SoC design, functional verification, and building wireless connectivity platforms and IoT products. He also holds two patents in … Read More


Synopsys Advances Hardware Assisted Verification for the AI Era

Synopsys Advances Hardware Assisted Verification for the AI Era
by Kalar Rajendiran on 03-26-2026 at 6:00 am

Software Defined HAV, Scalability, Density, Performance and EP Ready Hardware

At the 2026 Synopsys Converge Event, Synopsys announced a broad set of new products and platform upgrades, with its hardware-assisted verification (HAV) announcement emerging as a key highlight within that lineup. A key aspect of this announcement was moving beyond a hardware centric model to a more scalable, programmable … Read More


Securing UALink in AI clusters with UALinkSec-compliant IP

Securing UALink in AI clusters with UALinkSec-compliant IP
by Don Dingee on 03-24-2026 at 10:00 am

UALinkSec 200 Security Module block diagram

A classic networking problem is securing connections with encrypted data, but implementing strong encryption algorithms at wire speeds can limit performance. However, introducing blazing-fast connectivity without an encryption strategy leaves systems vulnerable. The architects in the UALink Consortium, including … Read More


Scaling Multi-Die Connectivity: Automated Routing for High-Speed Interfaces

Scaling Multi-Die Connectivity: Automated Routing for High-Speed Interfaces
by Kalar Rajendiran on 03-23-2026 at 10:00 am

Bump maps for HBM PHY and HBM memory

This article concludes the three-part series examining key methodologies required for successful multi-die design. The first article Reducing Risk Early: Multi-Die Design Feasibility Exploration focused on feasibility exploration and early architectural validation, while the second article Building the InterconnectRead More


Synopsys Explores AI/ML Impact on Mask Synthesis at SPIE 2026

Synopsys Explores AI/ML Impact on Mask Synthesis at SPIE 2026
by Mike Gianfagna on 03-16-2026 at 6:00 am

Synopsys Explores AI:ML Impact on Mask Synthesis at SPIE 2026

The SPIE Advanced Lithography + Patterning Symposium recently concluded. This is a popular event where leading researchers gather. Challenges such as optical and EUV lithography, patterning technologies, metrology, and process integration for semiconductor manufacturing and adjacent applications are all covered. This… Read More


Agentic AI and the Future of Engineering

Agentic AI and the Future of Engineering
by Daniel Nenni on 03-13-2026 at 6:00 am

sassine announces agentic ai hires converge 2026

Agentic AI emerges in this Synopsys Converge keynote not as a futuristic add-on, but as a practical response to the growing complexity of engineering. In the speaker’s view, the traditional way of designing chips, systems, and intelligent products is no longer sufficient for the era of physical AI. Engineers are now dealing with… Read More


Ravi Subramanian on Trends that are Shaping AI at Synopsys

Ravi Subramanian on Trends that are Shaping AI at Synopsys
by Daniel Nenni on 03-12-2026 at 8:00 am

Ravi Interview Synopsys Converge

Right before the Synopsys Converge Keynote I caught an interview with Ravi Subramanian, Chief Product Management Officer at Synopsys, which highlights several important trends shaping the future of AI, semiconductor technology, and engineering. His discussion focuses on how the worlds of silicon design and system engineering… Read More


Efficient Bump and TSV Planning for Multi-Die Chip Designs

Efficient Bump and TSV Planning for Multi-Die Chip Designs
by Daniel Nenni on 03-10-2026 at 6:00 am

Efficient Bump and TSV Planning for Multi Die Chip Designs

The semiconductor industry has experienced rapid advancements in recent years, particularly with the increasing demand for high-performance computing, artificial intelligence, and advanced automotive systems. Traditional single-die chip designs are often unable to meet modern PPA requirements. As a result, engineers… Read More


Reducing Risk Early: Multi-Die Design Feasibility Exploration

Reducing Risk Early: Multi-Die Design Feasibility Exploration
by Kalar Rajendiran on 03-05-2026 at 10:00 am

Feasibility Thermal Map

The semiconductor industry is entering a new era in system design. As traditional monolithic scaling approaches its economic and physical limits, multi-die architectures are emerging as a primary pathway for delivering continued improvements in performance, power efficiency, and integration density. By distributing … Read More


Building the Interconnect Foundation: Bump and TSV Planning for Multi-Die Systems

Building the Interconnect Foundation: Bump and TSV Planning for Multi-Die Systems
by Kalar Rajendiran on 03-03-2026 at 10:00 am

UCIe bump planning in 3DIC Compiler Platform

The first article in this series examined how feasibility exploration enables architects to evaluate multi-die system configurations while minimizing early design risk. Once architectural decisions are validated, designers must translate conceptual connectivity requirements into physical interconnect infrastructure.… Read More