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Ultra Ethernet and UALink IP solutions scale AI clusters

Ultra Ethernet and UALink IP solutions scale AI clusters
by Don Dingee on 12-19-2024 at 6:00 am

UALink and Ultra Ethernet roles in AI infrastructure clusters

AI infrastructure requirements are booming. Larger AI models carry hefty training loads and inference latency requirements, driving an urgent need to scale AI acceleration clusters in data centers. Advanced GPUs and NPUs offer solutions for the computational load. However, insufficient bandwidth or latency between servers… Read More


Synopsys Brings Multi-Die Integration Closer with its 3DIO IP Solution and 3DIC Tools

Synopsys Brings Multi-Die Integration Closer with its 3DIO IP Solution and 3DIC Tools
by Mike Gianfagna on 12-10-2024 at 6:00 am

Synopsys Brings Multi Die Integration Closer with its 3DIO IP Solution and 3DIC Tools

There is ample evidence that technologies such as high-performance computing, next-generation servers, and AI accelerators are fueling unprecedented demands in data processing speed with massive data storage, lower latency, and lower power. Heterogeneous system integration, more commonly called 2.5 and 3D IC design, … Read More


Enhancing System Reliability with Digital Twins and Silicon Lifecycle Management (SLM)

Enhancing System Reliability with Digital Twins and Silicon Lifecycle Management (SLM)
by Kalar Rajendiran on 12-09-2024 at 6:00 am

Synopsys SLM Solution Components

As industries become more reliant on advanced technologies, the importance of ensuring the reliability and longevity of critical systems grows. Failures in components, whether in autonomous vehicles, high performance computing (HPC), healthcare devices, or industrial automation, can have far-reaching consequences.… Read More


SystemReady Certified: Ensuring Effortless Out-of-the-Box Arm Processor Deployments

SystemReady Certified: Ensuring Effortless Out-of-the-Box Arm Processor Deployments
by Lauro Rizzatti on 12-05-2024 at 10:00 am

SystemReady Certified Ensuring Out of the Box Effortless Arm Processors Deployments Figure 1

When contemplating the Lego-like hardware and software structure of a leading system-on-chip (SoC) design, a mathematically inclined mind might marvel at the tantalizing array of combinatorial possibilities among its hardware and software components. In contrast, the engineering team tasked with its validation may have… Read More


A Master Class with Ansys and Synopsys, The Latest Advances in Multi-Die Design

A Master Class with Ansys and Synopsys, The Latest Advances in Multi-Die Design
by Mike Gianfagna on 12-04-2024 at 6:00 am

A Master Class with Ansys and Synopsys, The Latest Advances in Multi Die Design

2.5D and 3D multi-die design is rapidly moving into the mainstream for many applications. HPC, GPU, mobile, and AI/ML are application areas that have seen real benefits. The concept of “mix/match” for chips and chiplets to form a complex system sounds deceptively simple. In fact, the implementation and analysis techniques required… Read More


The Immensity of Software Development and the Challenges of Debugging Series (Part 4 of 4)

The Immensity of Software Development and the Challenges of Debugging Series (Part 4 of 4)
by Lauro Rizzatti on 11-19-2024 at 10:00 am

Immensity of SW development Part 4 Table 1

The Impact of AI on Software and Hardware Development

Part 4 of this series analyzes how AI algorithmic processing is transforming software structures and significantly modifying processing hardware. It explores the marginalization of the traditional CPU architecture and demonstrates how software is increasingly dominatingRead More


Synopsys-Ansys 2.5D/3D Multi-Die Design Update: Learning from the Early Adopters

Synopsys-Ansys 2.5D/3D Multi-Die Design Update: Learning from the Early Adopters
by Daniel Nenni on 11-06-2024 at 10:00 am

banner for webinar

The demand for high-performance computing (HPC), data centers, and AI-driven applications has fueled the rise of 2.5D and 3D multi-die designs, offering superior performance, power efficiency, and packaging density. However, these benefits come with myriads of challenges, such as multi-physics, which need to be addressed.… Read More


The Immensity of Software Development and the Challenges of Debugging (Part 3 of 4)

The Immensity of Software Development and the Challenges of Debugging (Part 3 of 4)
by Lauro Rizzatti on 10-03-2024 at 10:00 am

Immensity of SW development Part 3 Figure 1

Part 3 of this 4-part series analyzes methods and tools involved in debugging software at different layers of the software stack.

Software debugging involves identifying and resolving issues ranging from functional misbehaviors to crashes. The essential requirement for validating software programs is the ability to monitor… Read More


Synopsys and TSMC Pave the Path for Trillion-Transistor AI and Multi-Die Chip Design

Synopsys and TSMC Pave the Path for Trillion-Transistor AI and Multi-Die Chip Design
by Kalar Rajendiran on 10-02-2024 at 10:00 am

OIP 2024 Synopsys TSMC

Synopsys made significant announcements during the recent TSMC OIP Ecosystem Forum, showcasing a range of cutting-edge solutions designed to address the growing complexities in semiconductor design. With a strong emphasis on enabling next-generation chip architectures, Synopsys introduced both new technologies and … Read More


The Immensity of Software Development and the Challenges of Debugging Series (Part 2 of 4)

The Immensity of Software Development and the Challenges of Debugging Series (Part 2 of 4)
by Lauro Rizzatti on 09-25-2024 at 10:00 am

Immensity of SW development Part 2 Fig 1

Part 2 of this 4-part series reviews the role of virtual prototypes as stand-alone tools and their use in hybrid emulation for early software validation, a practice known as the “shift-left” methodology. It assesses the differences among these approaches, focusing on their pros and cons.

The Immensity of Software DevelopmentRead More