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Webinar: “Navigating our AI Wonderland” … with humans-in-the-Loop?

Webinar: “Navigating our AI Wonderland” … with humans-in-the-Loop?
by Richard Curtin on 12-06-2023 at 8:00 am

AIeverywhere EETimes

AI is here, there, and absolutely everywhere – now and forever.

The electronics industry, and the world at-large, have experienced an overwhelming amount of AI coverage this year, with no letup in store for 2024. Both EE Times and Silicon Catalyst have recently staged events around artificial intelligence:

  • AI Everywhere” delivered
Read More

RISC-V Summit Buzz – Axiomise Accelerates RISC-V Designs with Next Generation formalISA®

RISC-V Summit Buzz – Axiomise Accelerates RISC-V Designs with Next Generation formalISA®
by Mike Gianfagna on 12-04-2023 at 6:00 am

RISC V Summit Buzz – Axiomise Accelerates RISC V Designs with Next Generation formalISA®

If the recent RISC-V Summit proved one thing it’s that open-source hardware design, and particularly the RISC-V instruction set architecture (ISA) has entered the mainstream. It is a design methodology and architecture to watch closely. Across a broad range of applications from data center, to automotive, to IoT, RISC-V processors… Read More


RISC-V Summit Buzz – Semidynamics Founder and CEO Roger Espasa Introduces Extreme Customization

RISC-V Summit Buzz – Semidynamics Founder and CEO Roger Espasa Introduces Extreme Customization
by Mike Gianfagna on 11-30-2023 at 10:00 am

3d,Rendering,Of,Cyberpunk,Ai.,Circuit,Board.,Technology,Background.,Central

Founded in 2016 and based in Barcelona, Spain, Semidynamics™ is the only provider of fully customizable RISC-V processor IP.  The company delivers high bandwidth, high performance cores with vector units and tensor units targeted at machine learning and AI applications. There were some recent announcements from Semidynamics… Read More


WEBINAR : Avoiding Metastability in Hardware Software Interface (HSI) using CDC Techniques

WEBINAR : Avoiding Metastability in Hardware Software Interface (HSI) using CDC Techniques
by Daniel Nenni on 11-28-2023 at 10:00 am

Agnisys Mux Synchronizer

This webinar looks at the challenges a Design Engineer could face, such as when various IP blocks within an SoC are required to work in different clock domains to satisfy the power constraints.

Abstract:
Various IP blocks within an SoC are often required to work in different clock domains in order to satisfy the power constraints.… Read More


Siemens Digital Industries Software Collaborates with AWS and Arm To Deliver an Automotive Digital Twin

Siemens Digital Industries Software Collaborates with AWS and Arm To Deliver an Automotive Digital Twin
by Mike Gianfagna on 11-28-2023 at 6:00 am

Siemens Digital Industries Software Collaborates with AWS and ARM To Deliver an Automotive Digital Twin

 

According to McKinsey & Company, a digital twin is a digital representation of a physical object, person, or process, contextualized in a digital version of its environment. Digital twins can help an organization simulate real situations and their outcomes, ultimately allowing it to make better decisions. Anyone… Read More


Webinar: Silicon Catalyst & EE Times Examine the Bigger Picture Aspects of AI – Nov. 29, 2023 – 9am to 10am Pacific

Webinar: Silicon Catalyst & EE Times Examine the Bigger Picture Aspects of AI – Nov. 29, 2023 – 9am to 10am Pacific
by Mike Gianfagna on 11-20-2023 at 2:00 pm

Webinar Silicon Catalyst & EE Times Examine the Bigger Picture Aspects of AI – Nov. 29, 2023 – 9am to 10am Pacific

Artificial Intelligence (AI) is dominating the news cycle these days. It used to be about the latest (and largest) chips to accelerate AI algorithms. While that’s still relevant and exciting, AI news is taking a much broader, socioeconomic character. What does AI mean for job security, the economy, or even life on Earth? These … Read More


RISC-V Summit Buzz – Ron Black Unveils Codasip’s Paradigm Shift for Secured Innovation

RISC-V Summit Buzz – Ron Black Unveils Codasip’s Paradigm Shift for Secured Innovation
by Mike Gianfagna on 11-16-2023 at 10:00 am

Ron Black

Codasip is a processor solutions company with an expanding footprint. It is Europe’s leading RISC-V organization with a global presence. Codasip reports billions of chips already use its technology.  You can learn more about Codasip here, The company has made some announcements recently that expand its offerings in terms … Read More


IROC at the TSMC Open Innovation Ecosystem Platform

IROC at the TSMC Open Innovation Ecosystem Platform
by Daniel Nenni on 11-09-2023 at 6:00 am

TSMC OIP IROC

Radiation is everywhere. Radiation contributes to Single Event Effects (SEE) in semiconductor circuits and packaging. As chips get larger, containing more functions, and using lower voltage to reduce power, SEEs have become more significant to product reliability, Failures In Time rates (FIT), and meantime between failures… Read More


WEBINAR: Leverage Certified RISC-V IP to Craft ASIL ISO 26262 Grade Automotive Chips

WEBINAR: Leverage Certified RISC-V IP to Craft ASIL ISO 26262 Grade Automotive Chips
by Daniel Nenni on 11-07-2023 at 10:00 am

Webinar Image

The automotive industry imposes stringent requirements on Functional Safety. For semiconductor companies involved in automotive chips and even further upstream in Silicon Intellectual Property (SIP), obtaining ISO 26262 certification is a fundamental requirement for product penetration into automotive applications.… Read More


Webinar: Fast and Accurate High-Sigma Analysis with Worst-Case Points

Webinar: Fast and Accurate High-Sigma Analysis with Worst-Case Points
by Daniel Payne on 11-02-2023 at 10:00 am

Worst case point min

IC designers are tasked with meeting specifications like robustness in SRAM bit cells where the probability of a violation are lower than 1 part-per-billion (1 ppb). Another example of robustness is a Flip-Flop register that must have a probability of specification violation lower than 1 part-per-million (1 ppm). Using Monte… Read More