Physical Verification of 3D-IC Designs using TSVs

Physical Verification of 3D-IC Designs using TSVs
by Daniel Payne on 11-12-2011 at 10:36 am

3D-IC design has become a popular discussion topic in the past few years because of the integration benefits and potential cost savings, so I wanted to learn more about how the DRC and LVS flows were being adapted. My first stop was the Global Semiconductor Alliance web site where I found a presentation about how DRC and LVS flows were… Read More