The semiconductor industry creates increasingly complex SoC and chiplets using lots of IP and all of that IP needs to be characterized at the cell level. As we design with 3nm and 2nm nodes, the sheer volume of data required for accurate static timing analysis (STA) is greatly increasing. Modern design flows rely on characterized… Read More
Tag: Solido LibSPICE
Three New Circuit Simulators from Siemens EDA
The week before DAC I had the privilege to take a video call with Pradeep Thiagarajan – Product Manager, Simulation, Custom IC Verification at Siemens EDA to get an update on new simulation products. I’ve been following Solido for years now and knew that they were an early adopter of ML for Monte Carlo simulations with SPICE users.… Read More
