Navigating SoC Tradeoffs from IP to Ecosystem

Navigating SoC Tradeoffs from IP to Ecosystem
by Daniel Nenni on 12-17-2025 at 8:00 am

Building an SoC is Hard 2025

Building a complex SoC is a risky endeavor that demands careful planning, strategic decisions, and collaboration across hardware and software domains. As highlighted in Darren Jones’ RISC-V Summit presentation from Andes Technology, titled “From Blueprint to Reality: Navigating SoC Tradeoffs, IP, and Ecosystem,”… Read More


CAST’s Breakthrough in Automotive IP: The MSC-CTRL Microsecond Channel Controller

CAST’s Breakthrough in Automotive IP: The MSC-CTRL Microsecond Channel Controller
by Daniel Nenni on 12-10-2025 at 2:00 pm

CAST MSC CTRL SemiWiki

In a significant advancement for automotive electronics, Semiconductor intellectual property provider CAST has unveiled the MSC-CTRL Microsecond Channel Controller IP core. This new core empowers ASIC and FPGA designers with a deterministic, microsecond-precise serial interface for connecting to smart power and sensor… Read More


Chiplets: providing commercially valuable patent protection for modular products

Chiplets: providing commercially valuable patent protection for modular products
by Robbie Berryman on 08-24-2025 at 6:00 am

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Many products are assembled from components manufactured and distributed separately, and it is important to consider how such products are manufactured when seeking to provide commercially valuable patent protection. This article provides an example in the field of computer chip manufacture.

Chiplets

A system-on-a-chip

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Keysight at the 2025 Design Automation Conference #62DAC

Keysight at the 2025 Design Automation Conference #62DAC
by Daniel Nenni on 06-19-2025 at 10:00 am

62nd DAC SemiWiki

Keysight Showcases AI-Ready EDA and Multi-Physics Innovation at #62DAC

Design engineers attending #62DAC who focus on Design Data & IP Management, Analog, Mixed-Signal, RFIC, MMIC, or Multi-Physics should make booth #1408 a top destination. I had the opportunity to speak with Simon Rance, General Manager & Business… Read More


Breker Verification Systems at the 2025 Design Automation Conference #62DAC

Breker Verification Systems at the 2025 Design Automation Conference #62DAC
by Daniel Nenni on 06-02-2025 at 10:00 am

62nd DAC SemiWiki

Breker Verification Systems Plans Demonstrations of its Complete Synthesis and SystemVIP Library and Solutions Portfolio

Attendees who step into the Breker Verification Systems booth during DAC (Booth #2520—second floor) will see demonstrations of its Trek Test Suite Synthesis and SystemVIP libraries and solutions portfolio.… Read More


Voice as a Feature: A Silent Revolution in AI-Enabled SoCs

Voice as a Feature: A Silent Revolution in AI-Enabled SoCs
by Jonah McLeod on 05-26-2025 at 10:00 am

Voice as a Feature

When Apple introduced Siri in 2011, it was the first serious attempt to make voice interaction a mainstream user interface. Embedded into the iPhone 4S, Siri brought voice into consumers’ lives not as a standalone product, but as a built-in feature—a hands-free way to interact with an existing device. Siri set the expectation… Read More


2025 Outlook with Uzi Baruch of proteanTecs

2025 Outlook with Uzi Baruch of proteanTecs
by Daniel Nenni on 02-04-2025 at 6:00 am

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Tell us a little bit about yourself and your company. 

I am the Chief Strategy Officer at proteanTecs where I oversee our organic and inorganic growth strategies, as well as our go-to-market. This includes collaboration with ecosystem partners, defining our business model, and creating value for our customers through a targeted… Read More


Unlocking SoC Debugging Challenges: Paving the Way for Efficient Prototyping

Unlocking SoC Debugging Challenges: Paving the Way for Efficient Prototyping
by Daniel Nenni on 10-21-2024 at 10:00 am

3D rendering of cyberpunk AI. Circuit board. Technology background. Central Computer Processors CPU and GPU concept. Motherboard digital chip. Tech science background.

As chip design complexity increases, integration scales expand and time-to-market pressures grow, as a result, design verification has become increasingly challenging. In multi-FPGA environments, the complexity of design debugging and verification further escalates, making it difficult for traditional debugging methods… Read More


SmartDV at the 2024 Design Automation Conference

SmartDV at the 2024 Design Automation Conference
by Daniel Nenni on 06-19-2024 at 8:00 pm

DAC 2024 Banner

SmartDV’s presence at 61st DAC centers on connections, support, and the human side of IP. Over the past 18 months, we have been laser-focused on focused on overhauling and streamlining our customer support model to provide our global IP users with the best possible service. Vice President of Application Engineering Sergio Marchese… Read More


LIVE WEBINAR: Automating the Integration Workflow with IP Centric Design

LIVE WEBINAR: Automating the Integration Workflow with IP Centric Design
by Daniel Nenni on 04-09-2024 at 10:00 am

hip webinar automating integration workflow social

Subsystem and full-chip integration plays a crucial role in any project – particularly for large SoCs. Our upcoming webinar on April 30 confronts the typical challenges of this process and provides a detailed view into how IP centric  design can help you solve them. Join us to learn how transforming your design flow can help your… Read More