Webinar: Using Veloce PCD to implement an Arm CSS with confidence

Webinar: Using Veloce PCD to implement an Arm CSS with confidence
by Admin on 04-22-2025 at 10:09 am

Software Defines Everything
For today’s SoC and system designs, hardware is designed and optimized for the software workload. Workloads can include firmware, multi-OS architectures, AI/ML and complex graphics. These combined produce large software models that put pressure on system-level verification.

What is the Arm

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Webinar: Simplifying Interface Protocol Verification with Veloce Transactor Library

Webinar: Simplifying Interface Protocol Verification with Veloce Transactor Library
by Admin on 04-09-2025 at 2:36 am

As hyperscaler chiplet and SoCs grow in complexity, integrating and validating multiple high-speed and low-speed interface protocols—such as PCIe, CXL, UCIe, AMBA, AXI, AHB, CHI, CSI2, and DSI2, can be a significant challenge. Design Verification Engineers and Technical Managers must ensure seamless protocol compliance

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Webinar: Simplifying Interface Protocol Verification with Veloce Transactor Library

Webinar: Simplifying Interface Protocol Verification with Veloce Transactor Library
by Admin on 03-27-2025 at 1:04 pm

As hyperscaler chiplet and SoCs grow in complexity, integrating and validating multiple high-speed and low-speed interface protocols—such as PCIe, CXL, UCIe, AMBA, AXI, AHB, CHI, CSI2, and DSI2, can be a significant challenge. Design Verification Engineers and Technical Managers must ensure seamless protocol compliance

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Webinar: Tessent UltraSight-V – An on-chip debug and trace solution for RISC-V systems

Webinar: Tessent UltraSight-V – An on-chip debug and trace solution for RISC-V systems
by Admin on 03-24-2025 at 7:57 am

An infrastructure to enable debug and trace for your RISC-V systems is essential to identifying root-causing bugs. In this presentation, we will give an overview of Tessent UltraSight-V, an end-to-end RISC-V debug and trace solution consisting of embedded IPs and software that integrate with industry-standard tools.

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Webinar: Faster Debug of Complex Testbenches Using Visualizer

Webinar: Faster Debug of Complex Testbenches Using Visualizer
by Admin on 02-18-2025 at 1:45 pm

Wednesday, March 5 – 8:00 AM Pacific

Debugging testbenches can be a time-intensive challenge, but modern tools provide advanced features to simplify and accelerate the process.

This webinar will explore essential capabilities such as basic line stepping, dynamic variable monitoring, constraint debugging, and UVM

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Masterclass: Microsoft Focus on IP QA with Solido IP Validation Suite

Masterclass: Microsoft Focus on IP QA with Solido IP Validation Suite
by Admin on 02-04-2025 at 5:31 pm

Microsoft Focus on IP QA with Solido IP Validation Suite 

As System-on-Chip (SoC) designs grow increasingly complex, design IPs have become essential building blocks, promoting modularization and reusability. However, ensuring quality across vast IP libraries with diverse formats and views presents a significant challenge.

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