Tag: siemens

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Siemens and NVIDIA Expand Partnership to Build the Industrial AI Operating System

Siemens and NVIDIA Expand Partnership to Build the Industrial AI Operating System
by Daniel Nenni on 01-12-2026 at 6:00 am
Categories: AI, EDA, Siemens EDA

CES 2026 Jensen Huang founder and CEO of NVIDIA Roland Busch President and CEO of Siemens AG

At CES in Las Vegas, Siemens and NVIDIA announced a major expansion of their long-standing collaboration, aiming to create what they term the “Industrial AI Operating System.” This ambitious initiative seeks to embed artificial intelligence deeply across the entire industrial value chain—from design and engineering… Read More

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3D ESD verification: Tackling new challenges in advanced IC design

3D ESD verification: Tackling new challenges in advanced IC design
by Admin on 12-17-2025 at 10:00 am
Categories: 3D IC, EDA, Siemens EDA

fig1 3d structures

By Dina Medhat

Three key takeaways

  • 3D ICs require fundamentally new ESD verification strategies. Traditional 2D approaches cannot address the complexity and unique connections in stacked-die architectures.
  • Classifying external and internal IOs is essential for robust and cost-efficient ESD protection. Proper differentiation
… Read More

Webinar: Solving Timing closure challenges using Gencellicon (previously Excellicon)

Webinar: Solving Timing closure challenges using Gencellicon (previously Excellicon)
by Admin on 12-16-2025 at 6:16 pm

Timing closure is one of the most challenging aspects of ASIC design. While traditionally seen as a backend process, its resolution begins at the architectural level and extends through the implementation stages. This webinar examines the key obstacles designers encounter and demonstrates how our timing closure solutions

… Read More

Webinar: Automate PCB documentation with BluePrint-PCB

Webinar: Automate PCB documentation with BluePrint-PCB
by Admin on 12-02-2025 at 11:33 am

Streamlining fabrication and assembly documentation

  • December 9, 2025 at 06:00 AM Pacific Standard Time
  • December 9, 2025 at 01:00 PM Pacific Standard Time

BluePrint-PCB is a documentation automation tool that streamlines PCB fabrication, assembly, and inspection by generating intelligent, customizable electronic drawings

… Read More
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Why chip design needs industrial-grade EDA AI

Why chip design needs industrial-grade EDA AI
by Admin on 11-25-2025 at 10:00 am
Categories: EDA, Siemens EDA

EDA AI consumer vs industrial 72dpi

By Niranjan Sitapure

Artificial intelligence (AI) is reshaping industries worldwide. Consumer-grade AI solutions are getting significant attention in the media for their creativity, speed, and accessibility—from ChatGPT and Meta’s AI app to Gemini for image creation, Sora for video, Sona for music, and Perplexity for web… Read More

Webinar: Trained Eyes on 64G UCIe: Scale Chiplet Integration for AI

Webinar: Trained Eyes on 64G UCIe: Scale Chiplet Integration for AI
by Admin on 11-20-2025 at 3:10 am

Join us to hear firsthand from the innovators at Siemens and Alphawave Semi and learn proven practices to enhance your UCIe-enabled AI system performance!

The semiconductor industry is shifting rapidly from monolithic SoC design to chiplet-based systems. At the same time, AI compute workloads have pushed into petaflop-class

… Read More

Webinar: Don’t Let VHDL Debugging Slow You Down! Use Questa One Sim

Webinar: Don’t Let VHDL Debugging Slow You Down! Use Questa One Sim
by Admin on 10-29-2025 at 7:18 am

Join us for this essential webinar where we’ll explore how  Questa One Sim empowers VHDL designers to dramatically enhance their debugging productivity. We’ll move beyond basic simulation viewing and dive into advanced features designed to pinpoint issues faster, understand design behavior more intuitively,

… Read More

Webinar: HLV – Formal Verification of Synthesizable C++/SystemC Designs

Webinar: HLV – Formal Verification of Synthesizable C++/SystemC Designs
by Admin on 10-29-2025 at 7:15 am

High-Level Synthesis (HLS) is design flow in which design intent is described at a higher level of abstraction such as SystemC/C++/Matlab/etc. HLS tools are expected to synthesize this code to RTL which can be input to the traditional RTL downstream flow (RTL/GDS).

Formal check tools are difficult to be analyzed on generated

… Read More