Wednesday, May 28 – 8:00 AM Pacific
Managing traceability across multiple disconnected tools and data is a challenge that often leads to inefficiencies, missed coverage, and increased risk in safety-critical designs.
In this webinar, discover how Questa Verification IQ Testplan Author seamlessly integrates with
Wednesday, May 21 – 8:00 AM Pacific
The semiconductor industry faces a critical Verification Productivity Gap 2.0, driven by increasingly complex technologies including 3DICs, chiplet-based designs, and software-defined architectures.
This challenge is compounded by demands for Enhanced security, Reduced power
Software Defines Everything
For today’s SoC and system designs, hardware is designed and optimized for the software workload. Workloads can include firmware, multi-OS architectures, AI/ML and complex graphics. These combined produce large software models that put pressure on system-level verification.
What is the Arm
As hyperscaler chiplet and SoCs grow in complexity, integrating and validating multiple high-speed and low-speed interface protocols—such as PCIe, CXL, UCIe, AMBA, AXI, AHB, CHI, CSI2, and DSI2, can be a significant challenge. Design Verification Engineers and Technical Managers must ensure seamless protocol compliance
As hyperscaler chiplet and SoCs grow in complexity, integrating and validating multiple high-speed and low-speed interface protocols—such as PCIe, CXL, UCIe, AMBA, AXI, AHB, CHI, CSI2, and DSI2, can be a significant challenge. Design Verification Engineers and Technical Managers must ensure seamless protocol compliance
An infrastructure to enable debug and trace for your RISC-V systems is essential to identifying root-causing bugs. In this presentation, we will give an overview of Tessent UltraSight-V, an end-to-end RISC-V debug and trace solution consisting of embedded IPs and software that integrate with industry-standard tools.
We will… Read More
Debugging testbenches can be a time-intensive challenge, but modern tools provide advanced features to simplify and accelerate the process.
This webinar will explore essential capabilities such as basic line stepping, dynamic variable monitoring, constraint debugging, and UVM
Join us at Realize LIVE Europe 2025 and experience the energetic general sessions, the engaging Solutions Center and the insightful workshops.
See firsthand the Siemens Software community event and witness again where your digital transformation gets real. Fast.
Join our community of thinkers and doers in design, manufacturing, and lifecycle management to accelerate your digital transformation.
Detroit, Michigan | June 2-5, 2025
Registration opens Jan. 14, 2025.
Join our community of thinkers and doers in design, manufacturing,… Read More
Join us for the User2User North America event, which is a dedicated environment for exchanging ideas, information, and best practices that enable you to lead in your role and achieve success with your customers.
Santa Clara, CA | Santa Clara Marriott
May 20, 2025
Registration opens Feb. 10, 2025.
The User2User … Read More
