Join us for the User2User North America event, which is a dedicated environment for exchanging ideas, information and best practices that enable you to lead in your role and achieve success with your customers.
User2User is your opportunity to learn, grow and connect with fellow technical experts… Read More
By Dina Medhat
Three key takeaways
Timing closure is one of the most challenging aspects of ASIC design. While traditionally seen as a backend process, its resolution begins at the architectural level and extends through the implementation stages. This webinar examines the key obstacles designers encounter and demonstrates how our timing closure solutions
Streamlining fabrication and assembly documentation
BluePrint-PCB is a documentation automation tool that streamlines PCB fabrication, assembly, and inspection by generating intelligent, customizable electronic drawings
By Niranjan Sitapure
Artificial intelligence (AI) is reshaping industries worldwide. Consumer-grade AI solutions are getting significant attention in the media for their creativity, speed, and accessibility—from ChatGPT and Meta’s AI app to Gemini for image creation, Sora for video, Sona for music, and Perplexity for web… Read More
Join us to hear firsthand from the innovators at Siemens and Alphawave Semi and learn proven practices to enhance your UCIe-enabled AI system performance!
The semiconductor industry is shifting rapidly from monolithic SoC design to chiplet-based systems. At the same time, AI compute workloads have pushed into petaflop-class
Join us for this essential webinar where we’ll explore how Questa One Sim empowers VHDL designers to dramatically enhance their debugging productivity. We’ll move beyond basic simulation viewing and dive into advanced features designed to pinpoint issues faster, understand design behavior more intuitively,
High-Level Synthesis (HLS) is design flow in which design intent is described at a higher level of abstraction such as SystemC/C++/Matlab/etc. HLS tools are expected to synthesize this code to RTL which can be input to the traditional RTL downstream flow (RTL/GDS).
Formal check tools are difficult to be analyzed on generated
Traditional RTL low power design techniques such as sequential clock gating are widely deployed across the industry. Yet, even after multiple RTL revisions, residual power inefficiencies often remain undetected until silicon, resulting in missed optimization opportunities.
This seminar presents a refined approach to
By Mark Tawfik
Overview: Protecting ICs from costly ESD and latch-up failures
Electrostatic discharge (ESD) events cost the semiconductor industry an estimated $8 billion annually in lost productivity, warranty claims and product failures [1].
Ensuring the robust protection of integrated circuits (ICs) against various… Read More
