By Niranjan Sitapure
Artificial intelligence (AI) is reshaping industries worldwide. Consumer-grade AI solutions are getting significant attention in the media for their creativity, speed, and accessibility—from ChatGPT and Meta’s AI app to Gemini for image creation, Sora for video, Sona for music, and Perplexity for web… Read More
Join us to hear firsthand from the innovators at Siemens and Alphawave Semi and learn proven practices to enhance your UCIe-enabled AI system performance!
The semiconductor industry is shifting rapidly from monolithic SoC design to chiplet-based systems. At the same time, AI compute workloads have pushed into petaflop-class
Join us for this essential webinar where we’ll explore how Questa One Sim empowers VHDL designers to dramatically enhance their debugging productivity. We’ll move beyond basic simulation viewing and dive into advanced features designed to pinpoint issues faster, understand design behavior more intuitively,
High-Level Synthesis (HLS) is design flow in which design intent is described at a higher level of abstraction such as SystemC/C++/Matlab/etc. HLS tools are expected to synthesize this code to RTL which can be input to the traditional RTL downstream flow (RTL/GDS).
Formal check tools are difficult to be analyzed on generated
Traditional RTL low power design techniques such as sequential clock gating are widely deployed across the industry. Yet, even after multiple RTL revisions, residual power inefficiencies often remain undetected until silicon, resulting in missed optimization opportunities.
This seminar presents a refined approach to
By Mark Tawfik
Overview: Protecting ICs from costly ESD and latch-up failures
Electrostatic discharge (ESD) events cost the semiconductor industry an estimated $8 billion annually in lost productivity, warranty claims and product failures [1].
Ensuring the robust protection of integrated circuits (ICs) against various… Read More
RISC-V has emerged as a cornerstone of modern computing, offering an open-source alternative to proprietary designs like ARM and x86. Free from licensing fees and highly extensible, RISC-V powers everything from IoT devices to AI accelerators, with over 13 billion cores shipped globally. Annual RISC-V Summits, organized… Read More
The increasing demand for accelerated computing solutions calls for an agile hardware design methodology to be able to keep up with fast evolving landscape of algorithms. Traditional hardware design methodology has long development cycles involving defining architecture, doing microarchitecture development using RTL,
As digital chip design complexity grows, engineering teams face increasing pressure to meet aggressive PPA targets on tight schedules. To overcome this challenge, the EDA industry requires a revolutionary shift towards AI. Siemens EDA is leading this transformation by implementing a comprehensive strategy that combines… Read More
Ethernet speeds are accelerating fast and AI, Cloud, and HPC workloads are driving demand that doubles every year. With 800Gbps ports in production and 1.6Tbps Ethernet around the corner, the need for robust pre-silicon verification has never been greater.
Join this webinar to see how the Veloce™ hardware-assisted verification… Read More
