Tag: si/pi

Cadence TechTalk: Design Robust IC Packages Faster Using In-Design SI/PI Analysis

Cadence TechTalk: Design Robust IC Packages Faster Using In-Design SI/PI Analysis
by Admin on 04-17-2023 at 3:30 pm

IC package design teams and characterization teams have had a “throw-it-over-the-wall” relationship for decades, which often delays design releases by months. However, as signal integrity (SI) and power integrity (PI) challenges evolve with multi-die heterogeneous integration, the need to perform SI/PI analysis as part

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Technical Education Webinar Series: Three Issues Every EE Needs to Overcome to Sign Off on High-Speed PCB Designs

Technical Education Webinar Series: Three Issues Every EE Needs to Overcome to Sign Off on High-Speed PCB Designs
by Admin on 11-07-2022 at 3:03 pm

Sponsored by: Cadence

Presented by: Nitin Bhagwath, Director of Product Management

Event Duration: 60 minutes

Abstract:

Signal integrity/power integrity (SI/PI) are top priorities for engineers designing today’s high-speed, high-density circuit boards. Faster signoff of designs can be achieved by uncovering signal… Read More

Conquer SI/PI Challenges and Reduce Time to Signoff for PCIe 6.0

Conquer SI/PI Challenges and Reduce Time to Signoff for PCIe 6.0
by Admin on 05-18-2022 at 4:12 pm

Overview

The Peripheral Component Interconnect Express (PCIe®) high-speed interface has become the standard for computer expansion cards due to its high bandwidth combined with manageable component costs. However, the latest PCIe 6.0 release raises new challenges for design engineers, as the popular interface standard… Read More