22nd ACM/IEEE International Workshop on System-Level Interconnect Problems and Pathfinding (SLIP^2)

22nd ACM/IEEE International Workshop on System-Level Interconnect Problems and Pathfinding (SLIP^2)
by Daniel Nenni on 09-05-2020 at 8:00 am

GENERAL INFORMATION

The 2020 ACM/IEEE International Workshop on System-Level Interconnect Problems and Pathfinding (SLIP^2) is the 22nd, “rebooted” edition of the System-Level Interconnect Prediction (SLIP) Workshop. As computing systems and applications grapple with a post-Moore, post-CMOS, post-vonRead More


Pathfinding to an Optimal Chip/Package/Board Implementation

Pathfinding to an Optimal Chip/Package/Board Implementation
by Tom Dillinger on 02-04-2016 at 4:00 pm

A new term has entered the vernacular of electronic design engineering — pathfinding. The complexity of the functionality to be integrated and the myriad of chip, package, and board technologies available make the implementation decision a daunting task. Pathfinding refers to the method by which the design space of technology… Read More