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IC layout parasitics dominate the performance of custom digital, analog and mixed-signal designs, so the challenge becomes how to identify the root causes and to quantify the effects of parasitics during early design stages. The old method of iterating between layout, extraction, SPICE simulation, followed by manual debug… Read More
We are pleased to offer two webinar sessions for your convenience. Please choose the time that best fits your schedule:
10:00AM – 12:00PM CET (session #1 for EMEA/APAC)
10:00AM – 12:00PM PST (session #2 for NA)
Featured Speakers:
- Kopal Kulshreshtha, Principal Product Specialist, Synopsys
- Rob Dohanyos, Principal Product
…
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