Interconnect Watch: 3 Chip Design Merits for Network Applications

Interconnect Watch: 3 Chip Design Merits for Network Applications
by Majeed Ahmad on 10-21-2015 at 4:00 pm

The countdown to the end of Moore’s Law is coinciding with the rising complexity in system-on-chip (SoC) designs. And that’s not a mere coincidence. The leverage that has long been coming from shrinking process nodes in terms of cost, performance and power benefits is now increasingly being accomplished through… Read More