Tag: logic simulator

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Handling metastability during Clock Domain Crossing (CDC)

Handling metastability during Clock Domain Crossing (CDC)
by Daniel Payne on 11-22-2023 at 10:00 am
Categories: EDA, Siemens EDA

synchronizer min

SoC designs frequently have lots of different clock domains to help manage power more efficiently, however one side effect is that when the clock domains meet, i.e., in a Clock Domain Crossing (CDC), there’s the possibility of setup and hold time violations that can cause a flip-flop to become metastable. Synchronizer … Read More

Webinar: Introduction to Logic Simulator Programming Interfaces for FPGA Designs (Three Part Webinar Series) Part 2: The Power of VHDL’s VHPI (US)

Webinar: Introduction to Logic Simulator Programming Interfaces for FPGA Designs (Three Part Webinar Series) Part 2: The Power of VHDL’s VHPI (US)
by Admin on 04-03-2023 at 3:53 pm

Abstract:

The programming interfaces of logic simulators are largely the domain of specialists writing proprietary tools and extensions and are only vaguely in the consciousness of many design and verification engineers, if aware at all. Yet the simplest use of such interfaces opens up a whole world of possibilities in extending

… Read More