Configurable xSPI memory controller IP core is FuSa-ready

Configurable xSPI memory controller IP core is FuSa-ready
by Don Dingee on 05-13-2026 at 10:00 am

xSPI-MC block diagram

SPI, invented some four decades ago, is so successful as a low-pin-count interface for microcontrollers and processor cores that it spurred memory makers to incorporate both the physical signaling interface and advanced memory command protocols into serial flash and serial pseudo-SRAM (PSRAM) devices. Those protocols, … Read More


Renesas Scalable Automotive SoC Design Using Arteris NoC

Renesas Scalable Automotive SoC Design Using Arteris NoC
by Daniel Nenni on 04-14-2026 at 8:00 am

Arteris IP Renesas ADAS SoC

The increasing complexity of advanced driver assistance systems (ADAS) and automated driving architectures has driven a transition from traditional bus-based interconnects to scalable Network-on-Chip (NoC) fabrics. Renesas’ next-generation R-Car automotive SoC platforms adopt Arteris FlexNoC interconnect intellectual… Read More