Increase Efficiency and Reduce Risks with IC and Package Co-Design Flows

Increase Efficiency and Reduce Risks with IC and Package Co-Design Flows
by Admin on 06-16-2022 at 12:00 am

Date: Thursday, June 16, 2022

Time: 11:00am – 12:00pm (PDT)

Overview

System designers face increasing challenges in meeting technical specifications and time-to-market requirements. While process nodes continue to shrink, the complexity of packages continues to grow. Large pin counts of flipped and rotated ICs may… Read More


Increase Efficiency and Reduce Risks with IC and Package Co-Design Flows

Increase Efficiency and Reduce Risks with IC and Package Co-Design Flows
by Admin on 06-14-2022 at 12:00 am

Date: Tuesday, June 14, 2022

Time: 09:00 BST / 10:00 CEST / 11:00 EEST and Israel / 13:30 IST

System designers face increasing challenges to meet technical specification and time-to-market requirements. While process nodes continue to shrink, the complexity of packages continue to grow. Large pin counts of flipped and rotated

Read More

CadenceTECHTALK: Increase Efficiency and Reduce Risks with IC and Package Co-Design Flows – EMEAI

CadenceTECHTALK: Increase Efficiency and Reduce Risks with IC and Package Co-Design Flows – EMEAI
by Admin on 06-14-2022 at 12:00 am

EMEAI Session

Date: Tuesday, June 14, 2022

Time: 09:00 BST / 10:00 CEST / 11:00 EEST and Israel / 13:30 IST

System designers face increasing challenges to meet technical specification and time-to-market requirements. While process nodes continue to shrink, the complexity of packages continue to grow. Large pin counts of flipped

Read More

Webinar: Improving SI/PI Simulation of DDR Interfaces at the PCB/IC Package Level

Webinar: Improving SI/PI Simulation of DDR Interfaces at the PCB/IC Package Level
by Admin on 03-08-2020 at 9:00 am

Double data rate (DDR) synchronous dynamic random-access memory (SDRAM) is the common type of memory used as RAM for almost every modern processor. With DDR memory interface voltages decreasing, speeds increasing, and timing/power budgets being squeezed, design qualification using the latest memory interfaces is no small… Read More