CadenceTECHTALK: Preventing EM Failures in IC Designs with Signoff Analysis

CadenceTECHTALK: Preventing EM Failures in IC Designs with Signoff Analysis
by Admin on 08-29-2022 at 3:22 pm

Date: Tuesday, September 20, 2022

Time: 10:00 – 11:00 (CEST)

Electromigration (EM) impacts design reliability, causing failures over time. That is why it’s important to analyze both the power mesh and signal wires to check that the average, rms, or peak currents will not lead to a permanent failure. Learn how the Cadence

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Increase Efficiency and Reduce Risks with IC and Package Co-Design Flows

Increase Efficiency and Reduce Risks with IC and Package Co-Design Flows
by Admin on 05-20-2022 at 2:06 pm

Date: Thursday, June 16, 2022

Time: 11:00am – 12:00pm (PDT)

Overview

System designers face increasing challenges in meeting technical specifications and time-to-market requirements. While process nodes continue to shrink, the complexity of packages continues to grow. Large pin counts of flipped and rotated ICs may… Read More


CadenceTECHTALK: Increase Efficiency and Reduce Risks with IC and Package Co-Design Flows – EMEAI

CadenceTECHTALK: Increase Efficiency and Reduce Risks with IC and Package Co-Design Flows – EMEAI
by Admin on 05-20-2022 at 1:40 pm

EMEAI Session

Date: Tuesday, June 14, 2022

Time: 09:00 BST / 10:00 CEST / 11:00 EEST and Israel / 13:30 IST

System designers face increasing challenges to meet technical specification and time-to-market requirements. While process nodes continue to shrink, the complexity of packages continue to grow. Large pin counts of flipped

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Increase Efficiency and Reduce Risks with IC and Package Co-Design Flows

Increase Efficiency and Reduce Risks with IC and Package Co-Design Flows
by Admin on 05-18-2022 at 4:42 pm

Date: Tuesday, June 14, 2022

Time: 09:00 BST / 10:00 CEST / 11:00 EEST and Israel / 13:30 IST

System designers face increasing challenges to meet technical specification and time-to-market requirements. While process nodes continue to shrink, the complexity of packages continue to grow. Large pin counts of flipped and rotated

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Webinar: Improving SI/PI Simulation of DDR Interfaces at the PCB/IC Package Level

Webinar: Improving SI/PI Simulation of DDR Interfaces at the PCB/IC Package Level
by Admin on 02-20-2020 at 10:53 am

Double data rate (DDR) synchronous dynamic random-access memory (SDRAM) is the common type of memory used as RAM for almost every modern processor. With DDR memory interface voltages decreasing, speeds increasing, and timing/power budgets being squeezed, design qualification using the latest memory interfaces is no small… Read More