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Managing Test Power for ICsby Beth Martin on 11-07-2011 at 12:17 pmCategories: EDA, Siemens EDA
The goal for automatic test pattern generation (ATPG) is to achieve maximum coverage with the fewest test patterns. This conflicts with the goals of managing power because during test, the IC is often operated beyond its normal functional modes to get the highest quality test results. When switching activity exceeds a device’s… Read More