Webinar: Achieve Out-of-the-Box Equivalence Checking with Synopsys Formality ML-driven Distributed Processing

Webinar: Achieve Out-of-the-Box Equivalence Checking with Synopsys Formality ML-driven Distributed Processing
by Admin on 06-13-2023 at 3:31 pm

Synopsys Webinar | Wednesday, June 21, 2023 | 10:00 – 11:00 a.m. PDT

When designers synthesize chip designs with aggressive PPA targets, the expectation and goal is to be able to complete verification with minimal effort and a fast turn-around-time. Synopsys Design Compiler and Fusion Compiler offer a broad spectrum of

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Webinar: Fast and Accurate Functional ECOs with Synopsys Formality ECO

Webinar: Fast and Accurate Functional ECOs with Synopsys Formality ECO
by Admin on 08-10-2022 at 4:27 pm

Synopsys Webinar | Tuesday, August 16, 2022 | 8 a.m. Pacific

To achieve maximal quality of results (QoR) in synthesis, it requires leveraging retiming, multibit banking, and advanced datapath optimizations, which are part of the Synopsys Fusion Compiler™ implementation solution. However, during the late-stage functional

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LSI’s Experience With Formality Ultra

LSI’s Experience With Formality Ultra
by Paul McLellan on 08-26-2013 at 5:36 pm

LSI is an early adopter of Formality Ultra, Synopsys’s tool for improving the entire ECO flow. I already wrote about the basic capability of the tool here. ECOs are changes that come very late in the design cycle, after place and route has already been “nearly” completed. They occur either due to last minute spec… Read More


Formality Ultra, Streamline Your ECOs

Formality Ultra, Streamline Your ECOs
by Paul McLellan on 06-17-2013 at 8:00 am

One of the most challenging stages in an SoC design is achieving timing closure. Actually design closure is perhaps a better term since everything needs to come together such as clock tree, power nets, power budget and so on. Changes made to the design are known as ECOs (which stands for engineering change orders, a term that comes… Read More