Clock Design for SOCs with Lower Power and Better Specs

Clock Design for SOCs with Lower Power and Better Specs
by Daniel Payne on 12-15-2011 at 5:03 pm

Dan Ganousis posted in our SemiWiki forums about a newer technique to lower the power consumed by GHz clocks on SOC designs and asked if I was interested to learn more, so we met today via WebEx. Dan is with a company called Cyclos Semiconductor, co-founded in 2006 by Marios Papaefthymiou, President and Alexander Ishii, VP of Engineering.… Read More