CMOS 2.0 is Advancing Semiconductor Scaling

CMOS 2.0 is Advancing Semiconductor Scaling
by Daniel Nenni on 10-19-2025 at 10:00 am

CMOS 2.0

In the rapidly evolving landscape of semiconductor technology, imec’s recent breakthroughs in wafer-to-wafer hybrid bonding and backside connectivity are paving the way for CMOS 2.0, a paradigm shift in chip design. Introduced in 2024, CMOS 2.0 addresses the limitations of traditional CMOS scaling by partitioning… Read More


Advancements in High-Density Front- and Backside Wafer Connectivity: Paving the Way for CMOS 2.0

Advancements in High-Density Front- and Backside Wafer Connectivity: Paving the Way for CMOS 2.0
by Admin on 08-30-2025 at 6:00 am

Example of a possible partitioning of a SoC in the CMOS 2.0 era

In the rapidly evolving semiconductor landscape, imec’s recent breakthroughs in wafer-to-wafer hybrid bonding and backside technologies are reshaping the future of compute systems. As detailed in their article, these innovations transition CMOS 2.0 from a conceptual framework to practical reality, enabling denser,… Read More


SEMICON West- Jubilant huge crowds- HBM & AI everywhere – CHIPS Act & IMEC

SEMICON West- Jubilant huge crowds- HBM & AI everywhere – CHIPS Act & IMEC
by Robert Maire on 07-12-2024 at 6:00 am

Semicon West SF

– We just finished the most happy SEMICON West in a long time
– IMEC stole the show- HBM has more impact than size dictates
– Has Samsung lost its memory mojo? Is SK the new leader?
– AI brings new tech issues with it – TSMC is still industry King

Report from SEMICON West

The crowds at Semicon West were both… Read More