Transistor-Level Static Checking for Better Performance and Reliability

Transistor-Level Static Checking for Better Performance and Reliability
by Daniel Payne on 05-04-2021 at 10:00 am

power intent checks min

My first transistor-level IC design job was with Intel, doing DRAM designs by shrinking the layout to a smaller process node, and it also required running lots of SPICE runs with manually extracted parasitics to verify that everything was operating OK, meeting the access time specifications and power requirements across PVT … Read More


Together At Last—Combining Netlist and Layout Data for Power-Aware Verification

Together At Last—Combining Netlist and Layout Data for Power-Aware Verification
by Beth Martin on 09-25-2015 at 12:00 pm

The market demanded that gadgets it loves become ever more conscious of their power consumption, and chip designers responded with an array of clever techniques to cut IC power use. Unsurprisingly, these new techniques added to the complexity of IC verification. When you’re verifying a design that has 100+ separate power domains,… Read More


First Time, Every Time

First Time, Every Time
by SStalnaker on 01-21-2013 at 7:10 pm

While this iconic advertising phrase was first used to describe the ink reliability of a ballpoint pen, it perfectly summarizes the average consumer’s attitude toward automobile reliability as well. We don’t really care how it’s done, as long as everything in our car works first time, every time. Even when that includes heated… Read More