This webinar explores strategies for optimizing SMT filter designs, addressing spurious responses, parasitic behaviors, and PCB layout challenges using Cadence’s Microwave Office and Modelithics simulation models to ensure accurate and reliable performance.
Tag: CadenceTECHTALK
CadenceTECHTALK: PSpice-Based Reliability Analysis for Critical Systems
DATE: Wednesday, September 10, 2025
TIME: 8:00am PDT | 11:00am EDT | 3:00pm GMT | 8:30pm IST
In mission-critical sectors like aerospace, defense, and space systems, reliability is everything. Failures carry enormous risk, making rigorous design validation essential. This webinar explores how advanced PSpice simulation … Read More
CadenceTECHTALK: Quantus Insight: Intelligent Parasitic Debugging, Optimization, and Signoff Closure
Speaker: Kee Tat Ong, Principal Application Engineer
10:00am~11:00am Quantus Insight: Intelligent Parasitic Debugging, Optimization, and Signoff Closure
11:00am~11:15am Q&A
Description: With more designs migrating to advanced process nodes, chips are getting smaller, but design complexity is increasing in order… Read More
CadenceTECHTALK: iPegasus Verification System for Virtuoso Studio
Speaker: Hong-Cheang Quek, AE Director
10:00am~11:00am iPegasus Verification System for Virtuoso Studio
11:00am~11:15am Q&A
Description: Today’s complex SoC designs significantly increase layout creation and verification time, especially at advanced nodes. To meet overall demand for faster design cycle… Read More
CadenceTECHTALK: Next-generation Spectre FX FastSPICE Simulator and Spectre X Integration with GPU
Speaker: Soo Chuan Tang, Principal Application Engineer
10:00am~11:00am Next-Generation Spectre FX FastSPICE Simulator and Spectre X Integration with GPU
11:00am~11:15am Q&A
Description: Leveraging a FastSPICE engine built from the ground up, Cadence Spectre FX Simulator delivers performance and accuracy improvements… Read More
CadenceTECHTALK: Virtuoso ADE – MATLAB Integration and Co-Simulation with Spectre RF – MATLAB Simulink
Speaker: Bo Chen, Application Engineer Architect
10:00am~11:00 am Virtuoso ADE MATLAB Integration and Co-Simulation with Spectre RF MATLAB Simulink
11:00am~11:15 am Q&A
Description: Spectre and MATLAB/Simulink co-simulation provides the co-simulation using the Cadence Spectre simulator and the MATLAB/Simulink.… Read More
CadenceTECHTALK: Shift-Left Thermal Analysis with AI-Enabled Celsius Studio Platform
CadenceTECHTALK: AI-Driven 3D System Analysis and Optimization for EM Antenna/RF Problems
CadenceTECHTALK: Enabling RF and mmWave Design Success with Advanced Models
CadenceTECHTALK: High Performance Hierarchical IR Signoff for Large SoCs and 3D-ICs
Webinar Details
IR signoff for advanced SoCs and 3D-ICs is a major challenge due to extremely large and complex power networks that can exceed 100 billion nodes. Designers are faced with very long runtimes and very large compute resource requirements amounting to thousands of CPUs and 100TB+ memory to run a full-chip flat.
In this