One of the biggest surprises at the TSMC OIP Forum last week was the reappearance of bankrupt EDA vendor ATopTech. I spoke with former ATopTech CEO and now Avatar IS President Jue-Hsien Chern at OIP. As a survivor of several EDA legal battles myself, I understand what ATopTech went through and I am thoroughly impressed that they had… Read More
Tag: atoptech
ATopTech’s Legal Woes Continue!
It was a bad sign when an EDA company solicited John Cooley’s help in their legal challenge: See Did Atoptech Just Astroturf Synopsys? Gabe Moretti also did an article: John Cooley Barrister Chastises Synopsys | Gabe on EDA. An even worse sign is when your legal team gets disqualified, especially when that legal team is the top EDA… Read More
SPICE Timing Correlation for IC Place and Route
SPICE circuit simulation is used for transistor-level analysis while Place and Route tools are typically used to connect cells and blocks of an SoC, so why would there be a connection between these two EDA tools?
I read a press release today from ATopTech and Berkeley Design Automation that talked about how SPICE and P&R are … Read More