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Verification Engineer, Memory Protocols

Verification Engineer, Memory Protocols
by Admin on 06-18-2020 at 8:24 am

Achronix is a privately held fabless corporation based in Santa Clara, California and offers high-performance FPGA solutions. Achronix’s history is one of pushing the boundaries in the high-performance FPGA market. Achronix offerings include programmable FPGA fabrics, discrete high-performance and high-density FPGAs with hardwired system-level blocks, data center and HPC hardware accelerator boards, and best-in-class EDA software supporting all Achronix products.

 

The India Technology Center leads all SoC development at Achronix Semiconductor, working on end-to-end design development, from architecture development all the way to chip tape-out for Achronix’s Speedster and Speedcore class of FPGAs. The team owns the design of various high-speed SerDes, memory and NoC architecture subsystems, maximizing the data bandwidth and latency in and out of Achronix FPGAs.

Job Description/Responsibilities

The opening is for a verification engineer who is responsible for the verification of memory subsystems that go into Achronix’s Speedster class of FPGAs. These include high-speed, cutting-edge protocols such as DDR5, GDDR6 and HBM2/2e. This employee will be responsible for module- and integration-level RTL verification, as well as performance modeling. This employee is expected to take independent ownership of complex design challenges. The primary responsibilities include:

  • Create verification test plans
  • Functional verification at module, subsystem, and full chip levels
  • Testbench design
  • ATE functional vector generation
  • Post-Si support
  • Participate in the review of other designs’ verification
  • Contribute to verification methodologies and best practices

This employee is also expected to participate regularly in interactions with global teams spanning systems, software and product engineering

Skills

  • Expertise with DRAM interfaces and verification
  • Expertise in verification methodologies, especially UVM or CRV
  • Strong automation and scripting experience, especially in Python and/or Perl
  • Experience with post-Si bring-up and debug
  • Strong verbal and written communication skills
  • Ability to work in a dynamic and fast-paced environment, with a proactive mindset
  • Prior experience with providing technical mentoring to junior engineers is a plus
  • Experience with formal verification tools is a plus

Education and Experience

  • Preferred BS/MS plus 6-12 years of experience in RTL design and verification
  • At least four years of experience in SerDes protocols’ design verification
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