Staff SoC Verification Engineer

At Innatera we are committed to driving innovation and delivering exceptional results while creating an environment where our teams can thrive. We are a group of passionate, creative thinkers who thrive in a fast-paced environment on challenges and are always ready to take on the next big thing.

As a valued member of our team focused on making a positive impact, your unique contributions play a significant role in creating meaningful change. Working alongside a talented group of colleagues, you will experience a supportive environment that recognizes and values your life beyond the confines of work.

We will trust you with:

• Develop and maintain SystemVerilog/UVM-based verification environments at both module and SoC level;
• Write test sequences, define functional coverage models, and ensure coverage closure;
• Debug simulation results using waveform tools and collaborate with design teams to resolve issues;
• Drive constrained-random stimulus generation and continuous improvements in our verification methodology;
• Apply modern EDA tools and automate verification flows to maximize speed and quality;
• Contribute to quality assurance, release-readiness, and design-test alignment for every chip.

What you’ll need to succeed:

• 8+ years of digital verification, including 4+ years of constrained-random verification with UVM.
• 2+ years of embedded C development for SoC verification.
• Experience designing verification architecture from design specifications and creating test plans.
• Ability to translate functional requirements into functional coverage models.
  Skilled in constrained-random stimulus generation and coverage analysis/closure.
• Strong expertise in root-cause analysis and debugging SystemVerilog RTL.
• Proficiency in scripting with Python or similar languages.
• Solid experience with Linux, bash, or equivalent environments.
• Proficient with commercial EDA tools.
• Experience collaborating effectively with cross-functional teams.
• Hands-on experience with UVM verification architecture and vertical reuse of lower-level UVCs/environments.
• Skilled in mixed-language simulation and system modeling.
• Experience with effort estimation, project planning, scheduling, and tracking.
• Proven ability to lead and mentor a small team.

Nice-to-haves:

• Experience with SystemC for modeling and simulation.
• Knowledge of UPF and low-power verification methodologies.
• Exposure to formal verification techniques.
• Hands-on experience with FPGA validation and bring-up.
• Experience with full-chip emulation and bring-up.
• Familiarity with OpenOCD/GDB for software-driven verification.
• Experience in SystemVerilog RTL design.

Why join Innatera?
At Innatera, you’ll be part of a pioneering team building the next generation of brain-inspired processors for edge AI. Your work will help bring groundbreaking technology to life, powering intelligent devices with real-world impact, from healthcare to consumer electronics.

• Competitive salary.
• Pension plan.
• A flexible working environment (work-from-home policy, flexible working hours, advantageous holidays scheme) Note: We work from the office 3 days per week if you want to work in The Netherlands, or, you can work fully remotely for this role.
• A generous holiday scheme.
• A collaborative, ambitious team with the freedom to innovate
• An inclusive culture that values openness, curiosity, and personal growth
• Office perks like fresh fruit, snacks, and an on-site gym
• Statutory commuting/home allowance