Senior Hardware Design Engineer
Website ArterisIP
Arteris enables engineering and design teams at the world’s most transformative brands to connect and integrate today’s system-on-chips (SoCs) that fuel modern innovation.
If you’ve held a smartphone, driven an electronic car, or powered up a smart TV, you’ve come in contact with what we do at Arteris. Here, the future is quite literally in your hands—and when it isn’t, chances are it is flying overhead in a drone, a satellite, or in the cloud at a datacenter!
The role consists of managing the development of ARTERIS hardware components, and ensuring that they are delivered on time and to the required quality. He/she is responsible for the design of an entire system, and provides technical support to a group of hardware design engineers. He supports customer discussions and is the interface with application engineering.
Your major activities will :
- Lead the hardware design of configurable IPs and write architecture specifications for highly configurable networks-on-chips, respecting the most stringent coverage requirements in design verification.
- Contribute to the design of hardware blocks and ensure their quality
- Participate in the verification methodology and regression environment.
- Communicate with hardware and software teams to ensure product cohesion.
- Maintain and improve existing versions in collaboration with the application engineering team.
- Support technical discussions with customers.
- Report synthetically on development progress
Qualifications and experiences required :
- 8+ years of experience in SoC/IP/NoC designs,
- Expert in coherent and non-coherent communication protocols and control models (AMBA, PCIe, CXL, OCP, others).
- Expert in CPU architectures (ARM/RISC V).
- Strong experience in SoC/IP design flow (e.g. specification, architecture, RTL coding, verification, DFT, synthesis, compliance with power and frequency constraints).
- Excellent problem solving, strong communication and teamwork skills,
- Expertise in SystemC, Verilog/VHDL/System Verilog, Cadence/Synopsys/Mentor Graphic (backend tools), C++, Python, scripting languages.
- Fluenty English
Education Requirement: Master’s degree or Doctorate in engineering or computer science
Base Salary: depending qualification and experience between 50 to 65 KE / year
Apply for job
To view the job application please visit www.arteris.com.
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