DFT Engineer
Descriptions
- Complete DFT logic design, including: memory BIST, memory BISR, scan insertion, boundary scan insertion, macro testing.
- Complete DFT mode timing constraint, support DFT mode timing closure.
- Support chip bring-up, complete test pattern debugging, yield improvement.
- Provide technical support for customer/FAE/sales.
Requirements
- Master of EE or above, work experience and rank are not limited.
- Study hard and work actively.
- Have following single or multiple experiences: chip level testing, ASIC coding and simulation, design implementation from RTL to GDS.
- Full of enterprise and the spirit of teamwork, good ability to communicate and express, fluent in Mandarin and English.
MediaTek Develops Chip Utilizing TSMC’s 2nm Process, Achieving Milestones in Performance and Power Efficiency