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F
3D DRAM does not require EUV:
AI Overview
No, 3D DRAM does not inherently require EUV lithography; in fact, the vertical stacking of...
Sep 30, 2025
F
DRAM really is in difficult situation. Some companies are planning 1d or 1e DRAM (but since their 1c is already in 11nm class...
Sep 30, 2025
F
There was the NUMMI at Fremont, CA. If 14A doesn't go well, we may see its semiconductor equivalent.
Sep 30, 2025
S
DRAM really is in difficult situation. Some companies are planning 1d or 1e DRAM (but since their 1c is already in 11nm class...
Sep 30, 2025
B
3D DRAM does not require EUV:
AI Overview
No, 3D DRAM does not inherently require EUV lithography; in fact, the vertical stacking of...
Sep 30, 2025
C
Always a good thing when people have to invent terms like "circular financing" to describe a business strategy, I feel like I've seen...
Sep 30, 2025
S
I was looking over some of Intel's recent SPIE papers from within the past year. ASML/Zeiss can't measure the High-NA EUV system...
Sep 30, 2025
S
It might not say "nm" any more but that's what most non-techie people *think* it means -- and as for Intel's "18A", don't get me...
Sep 30, 2025
S
From my notes:
TSMC N7 is DUV, TSMC N7+ uses 4 EUV layers, TSMC N6 uses 5 EUV layers, TSMC N5 uses 14 EUV layers.
AMD and HiSilicon...
Sep 30, 2025
S
N7 was all-DUV, N7P had some EUV layers but incompatible design rules so no IP porting. IIRC (we didn't use it) N6 was a shrunk N7 (with...
Sep 30, 2025
S
The thinning of the dielectric between bit line and storage node contact results in rapidly growing parasitic capacitances and leakage...
Sep 30, 2025
F
I was looking over some of Intel's recent SPIE papers from within the past year. ASML/Zeiss can't measure the High-NA EUV system...
Sep 30, 2025
I
It might not say "nm" any more but that's what most non-techie people *think* it means -- and as for Intel's "18A", don't get me...
Sep 30, 2025
S
yes but it's not referring to nm
Yeah but good luck explaining that many numbers to people and not to mention TSMC/Samsung/Intels node...
Sep 30, 2025
I
Yes, but it's still fictional isn't it?
In N2 you can draw a 3nm gate but we know the physical gate length needed to control the GAA...
Sep 30, 2025
Like.
3D DRAM does not require EUV: AI Overview No, 3D DRAM does not inherently require EUV lithography; in fact, the vertical stacking of...
Wow.
I was looking over some of Intel's recent SPIE papers from within the past year. ASML/Zeiss can't measure the High-NA EUV system...