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S
I was looking over some of Intel's recent SPIE papers from within the past year. ASML/Zeiss can't measure the High-NA EUV system...
Sep 30, 2025
S
It might not say "nm" any more but that's what most non-techie people *think* it means -- and as for Intel's "18A", don't get me...
Sep 30, 2025
S
From my notes:
TSMC N7 is DUV, TSMC N7+ uses 4 EUV layers, TSMC N6 uses 5 EUV layers, TSMC N5 uses 14 EUV layers.
AMD and HiSilicon...
Sep 30, 2025
S
N7 was all-DUV, N7P had some EUV layers but incompatible design rules so no IP porting. IIRC (we didn't use it) N6 was a shrunk N7 (with...
Sep 30, 2025
S
The thinning of the dielectric between bit line and storage node contact results in rapidly growing parasitic capacitances and leakage...
Sep 30, 2025
F
I was looking over some of Intel's recent SPIE papers from within the past year. ASML/Zeiss can't measure the High-NA EUV system...
Sep 30, 2025
I
It might not say "nm" any more but that's what most non-techie people *think* it means -- and as for Intel's "18A", don't get me...
Sep 30, 2025
S
yes but it's not referring to nm
Yeah but good luck explaining that many numbers to people and not to mention TSMC/Samsung/Intels node...
Sep 30, 2025
I
Yes, but it's still fictional isn't it?
In N2 you can draw a 3nm gate but we know the physical gate length needed to control the GAA...
Sep 30, 2025
S
at least even marketing moved to N7/6/5/4/3/2 and I7/4/3/18A
Sep 30, 2025
F
Indeed -- but the other key point is how many layers EUV is used on, and in newer processes how many separate EUV masks are used...
Sep 30, 2025
I
Just like "5nm" and "4nm" and "3nm" and "2nm" then... ;-)
Sep 30, 2025
I
TSMC N6 and TSMC N5 came out at the same time (Q1 2020). TSMC considers N7, N7+ and N6 one node, that is how they report it. Same with...
Sep 30, 2025
I
Indeed -- but the other key point is how many layers EUV is used on, and in newer processes how many separate EUV masks are used...
Sep 30, 2025
S
OpenAI Hyperscaler with chips on loan from Nvidia 🤣 🤣
Sep 30, 2025
Wow.
I was looking over some of Intel's recent SPIE papers from within the past year. ASML/Zeiss can't measure the High-NA EUV system...
Like.
It might not say "nm" any more but that's what most non-techie people *think* it means -- and as for Intel's "18A", don't get me...