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B
1c uses EUV as well:
AI overview:
SK hynix:
This company is a leader in EUV adoption for DRAM, utilizing five or more EUV layers for...
Sep 29, 2025
B
When I looked at the chart for ASML, I think Barrons is wrong, you'd be happy to own ASML and enjoy the tailwind of a weaker dollar on...
Sep 29, 2025
TSMC N6 and TSMC N5 came out at the same time (Q1 2020). TSMC considers N7, N7+ and N6 one node, that is how they report it. Same with...
Sep 29, 2025
S
I can bet someone must be planning in WH to reduce this reliance but how successful will that be only time can tell.
Sep 29, 2025
S
And then they have to chose: to die or to find ways to work with TSM in TW.
Sep 29, 2025
P
And then they have to chose: to die or to find ways to work with TSM in TW.
Sep 29, 2025
S
OK, my first speculation was wrong then (but my second one wasn't!) -- note the comment about backward-compatible design rules which was...
Sep 29, 2025
OK, my first speculation was wrong then (but my second one wasn't!) -- note the comment about backward-compatible design rules which was...
Sep 29, 2025
I
OK, my first speculation was wrong then (but my second one wasn't!) -- note the comment about backward-compatible design rules which was...
Sep 29, 2025
Yes I am sure. Would you dare to question Scotten Jones? ;)
From TSMC:
EUV process improves logic density; provides backward...
Sep 29, 2025
S
i was seeing rumors that N3 and N2 had the same EUV layers count and those seemed false thanks for the confirmation :) as for N2 expense...
Sep 29, 2025
S
If you think N3 was bad for EUV layers (and wafer prices!), you shouldn't even look at N2... ;-)
Sep 29, 2025
I
If you think N3 was bad for EUV layers (and wafer prices!), you shouldn't even look at N2... ;-)
Sep 29, 2025
I
Are you absolutely sure about N6? As I said we never used it, but I'm pretty sure it was a linear shrink and cost reduction of N7, not...
Sep 29, 2025
I
I should hope I was right, what I said was based on actual PDK and layouts, not TSMC (or any other) website... ;-)
Sep 29, 2025
Daniel Nenni replied to the thread Intel splashes more cash on ASML’s magic machines.TSMC N6 and TSMC N5 came out at the same time (Q1 2020). TSMC considers N7, N7+ and N6 one node, that is how they report it. Same with...
Like.
And then they have to chose: to die or to find ways to work with TSM in TW.
Haha.
If you think N3 was bad for EUV layers (and wafer prices!), you shouldn't even look at N2... ;-)