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I
The problem for Intel is that it's increasingly difficult for any IDM to compete with TSMC as far as process/IP/PDCO is concerned -- not...
Aug 20, 2025
S
China has a lot of customers. SMIC's ecosystem isn't as large as TSMC's but there are plenty of clients with advanced designs...
Aug 20, 2025
C
Never say never. The reason I have confidence in this is the slowdown in the pace of Moore's law. If leading edge was still doubling...
Aug 20, 2025
S
The problem was at the chip level, where read latency was about 350ns, which poorly compares to DRAM. I think write latency was in the...
Aug 20, 2025
Could Mr. Pat Gelsinger invite Jensen Huang, Lisa Su, Tim Cook, and CC Wei, each separately, for a personal dinner? He could use the...
Aug 20, 2025
S
Over-sold by the team leadership, under performed compared to performance targets (latency was higher than projected), lack of...
Aug 20, 2025
T
Well, everyone is underestimating China...
No, not just China, there is a tendency to underestimate newcomers with momentum.
The same...
Aug 20, 2025
S
If we look back, Intel has missed many incredible opportunities over the years. I would argue that this is the inevitable result of...
Aug 20, 2025
I
"...delivering the highest performance and fastest memory bandwidth among comparable Intel processors in the cloud."
Note lack of...
Aug 20, 2025
No; the vertical order of layers in a packaged chip is as follows:
FSPD (conventional, die face down)
1. heatsink (top)
2. TIM
3. thick...
Aug 20, 2025
@IanD what happens to a BSPDN Chip for example an Intel 18A CPU running 6+ GHz do you think traditional cooling will be able to...
Aug 20, 2025
Like I said, AI/HPC/GPU/CPU are applications for which BSPD is suitable (and targeted at), given a decent heatsink -- meaning not LN2...
Aug 20, 2025
I
Like I said, AI/HPC/GPU/CPU are applications for which BSPD is suitable (and targeted at), given a decent heatsink -- meaning not LN2...
Aug 20, 2025
S
@IanD what happens to a BSPDN Chip for example an Intel 18A CPU running 6+ GHz do you think traditional cooling will be able to...
Aug 20, 2025
P
Everyone is making same chips: DSP array, SRAM, DDR/HBM phy and some fast IO. Sometimes it looks like just different SKU's of same...
Aug 20, 2025
Like.
The problem was at the chip level, where read latency was about 350ns, which poorly compares to DRAM. I think write latency was in the...
hist78 replied to the thread Opinion: To make IDM 3.0 a success, Intel must make other companies IDM.Could Mr. Pat Gelsinger invite Jensen Huang, Lisa Su, Tim Cook, and CC Wei, each separately, for a personal dinner? He could use the...
Daniel Nenni reacted to IanD's post in the thread How are the benefits of BSPD affected by 3D stacking? with