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fwiw, Intel is doing multiple compute tile arrangements on Server (1, 2, or 3), but not on any hybrid architectures (e+p core) yet:
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cache coherency issues L3 have to be connected through some fabric and they have to use interconnect to connect two different tiles with...
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we can but that can only be done sometimes in end of 2026 or 2027
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Ok. Could we then measure the performance of the p-core by 18a and the p-core by tsmc? Hopefully that at least shed some light on 18a...
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Yeah but the DMs have no way to send Images so i couldn't explain properly :ROFLMAO: :ROFLMAO:
so AMD uses two Core complex(CCX) aka...
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We kind of forget don’t we - the first few iPhone app processors were just modified Samsung app processors, until the Apple-designed A4...
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The 2005-2008 timeline showed a lot of bad decisions related to mobile, both for Intel and AMD.
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