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Any indications of what "transistor performance class" the SMIC node would be? (current, leakage, etc)
Sunday at 9:57 PM
B
Is Intel working on a sign language interpreter?
Sunday at 6:35 PM
S
Maybe it's also as a TSMC's strategy to kill off Rapidus before its birth?
Sunday at 5:42 PM
Is it possible AMD has customer(s) demanding a second source?
Sunday at 1:51 PM
You heard it here first: AMD $AMD is planning to use Intel $INTC foundry to manufacture chips in the USA (not just packaging). During my...
Sunday at 1:51 PM
S
very likely AMD needs to and has to do some exploration with Intel, while majority business now and in foreseeable future are still with...
Sunday at 11:26 AM
S
thanks great info. For design point, BTC is not using higher Vdd due to overall power constraints? what was constraining it, DC cooling?
Sunday at 11:25 AM
B
This article explained that some discrepancies may arise, depending on the layout assumptions, such as the ratio of NAND to Flip-Flop...
Sunday at 11:14 AM
B
N+2 is 93 mtr.
It has 63nm gate pitch and 252nm cell height which revealed by Techinsight.
118 mtr mean ~27% density improve, very huge.
Sunday at 11:12 AM
B
TechInsights has completed an exploratory teardown and process analysis of the Huawei Kirin 9030 application processor used in the new...
Sunday at 11:07 AM
This is a pretty awesome list -- siliconbruh -- do you have offline data for older CPUs?
It would be fun to graph a 'downward trend'...
Sunday at 10:53 AM
Any indications of what "transistor performance class" the SMIC node would be? (current, leakage, etc)
Sunday at 10:39 AM
Actually TSMC N7 to N5 M2 pitch shrink (40 nm to 35 nm) wasn't enough by itself to justify a node change. Gate pitch shrink was also...
Sunday at 10:38 AM
It seems like N+3 is truly G57H228 ( come from Techinsight decap data).
Hard to judge whether this is 5nm or not.
Techinsight think...
Sunday at 10:38 AM
Hard to believe AMD would give up first class flying at TSMC. They can make wafers at TSMC in AZ all day long. I bet TSMC AZ will double...
Sunday at 9:39 AM
Like.
Any indications of what "transistor performance class" the SMIC node would be? (current, leakage, etc)
Xebec replied to the thread AMD Job Listing Suggests Partnership with Intel Foundry.Is it possible AMD has customer(s) demanding a second source?
Daniel Nenni replied to the thread AMD Job Listing Suggests Partnership with Intel Foundry.Hard to believe AMD would give up first class flying at TSMC. They can make wafers at TSMC in AZ all day long. I bet TSMC AZ will double...