Daniel Payne
Moderator
The Xyce (TM) team is pleased to announce the release of Xyce (TM)
Version 6.4. This release fixes a number of bugs in Xyce (TM) 6.3
and includes improvements to existing features of Xyce (TM) 6.4. Please
see the Release Notes for a complete list of new features and enhancements.
Highlights for Xyce Release 6.4 include:
New Devices and Device Model Improvements
* VBIC version 1.3, 3- and 4-terminal variants (Q levels 11 and 12)
* MEXTRAM 504.11 with self-heating (Q level 505)
* New memristor device using the Yakopcic model
* Support for Reactive Power limits in the Power Grid Generator Bus model.
Enhanced Solver Stability, Performance and Features
* The Kundert SPARSE linear solver has been added as a linear solver option.
* The netlist parser has been significantly refactored to reduce memory
consumption and improve parsing speeds for large circuits.
* Improved Harmonic Balance (HB) robustness during the initial guess
calculation.
* New Local truncation Error (LTE) criterions that use history information
of signals improve time stepping for all time integrators.
* Oversampling capability for Harmonic Balance time domain output enables
users to produce well-resolved time-domain outputs.
* Arclength continuation is now much more useful and robust.
* Sensitivity analysis can now allow multiple objective functions.
Interface Improvement
* Power calculations supported for controlled-source devices (B,E,F,G and H).
* Support for additional .MEASURE statement syntaxes.
* New output options, that allow the user to suppress the header and
footer of standard-format output files.
* Improved error handling during netlist parsing.
* Improved Harmonic Balance Output.
* Improved compatibility between Xyce (TM) and PSpice Digital Behavioral
models, via support for the DIGINITSTATE option which sets the initial
state of the Digital Flip-Flip and Latch devices.
For details, see the Xyce(TM) Users' Guide and the Xyce(TM) Reference
Guide.
Also associated with this release are updates to the web site. The
Frequently Asked Questions page has also been updated.
To obtain a copy of Xyce(TM) Release Version 6.4, please see the
downloads section of the web site: Sandia National Laboratories: Xyce Parallel Electronic Simulator (Xyce): Sign-in
The team actively participates in an open forum for discussion of Xyce
on Google Groups. Details on how to join this forum are on the
Documentation and Tutorials page of the web site,
Sandia National Laboratories: Xyce Parallel Electronic Simulator (Xyce): Documentation & Tutorials.
Thank You,
The Xyce(TM) Team
Version 6.4. This release fixes a number of bugs in Xyce (TM) 6.3
and includes improvements to existing features of Xyce (TM) 6.4. Please
see the Release Notes for a complete list of new features and enhancements.
Highlights for Xyce Release 6.4 include:
New Devices and Device Model Improvements
* VBIC version 1.3, 3- and 4-terminal variants (Q levels 11 and 12)
* MEXTRAM 504.11 with self-heating (Q level 505)
* New memristor device using the Yakopcic model
* Support for Reactive Power limits in the Power Grid Generator Bus model.
Enhanced Solver Stability, Performance and Features
* The Kundert SPARSE linear solver has been added as a linear solver option.
* The netlist parser has been significantly refactored to reduce memory
consumption and improve parsing speeds for large circuits.
* Improved Harmonic Balance (HB) robustness during the initial guess
calculation.
* New Local truncation Error (LTE) criterions that use history information
of signals improve time stepping for all time integrators.
* Oversampling capability for Harmonic Balance time domain output enables
users to produce well-resolved time-domain outputs.
* Arclength continuation is now much more useful and robust.
* Sensitivity analysis can now allow multiple objective functions.
Interface Improvement
* Power calculations supported for controlled-source devices (B,E,F,G and H).
* Support for additional .MEASURE statement syntaxes.
* New output options, that allow the user to suppress the header and
footer of standard-format output files.
* Improved error handling during netlist parsing.
* Improved Harmonic Balance Output.
* Improved compatibility between Xyce (TM) and PSpice Digital Behavioral
models, via support for the DIGINITSTATE option which sets the initial
state of the Digital Flip-Flip and Latch devices.
For details, see the Xyce(TM) Users' Guide and the Xyce(TM) Reference
Guide.
Also associated with this release are updates to the web site. The
Frequently Asked Questions page has also been updated.
To obtain a copy of Xyce(TM) Release Version 6.4, please see the
downloads section of the web site: Sandia National Laboratories: Xyce Parallel Electronic Simulator (Xyce): Sign-in
The team actively participates in an open forum for discussion of Xyce
on Google Groups. Details on how to join this forum are on the
Documentation and Tutorials page of the web site,
Sandia National Laboratories: Xyce Parallel Electronic Simulator (Xyce): Documentation & Tutorials.
Thank You,
The Xyce(TM) Team