You are currently viewing SemiWiki as a guest which gives you limited access to the site. To view blog comments and experience other SemiWiki features you must be a registered member. Registration is fast, simple, and absolutely free so please, join our community today!
It seems TSM has seized the lead over Samsung in part through superior packaging using InFO packaging versus the more standard FoWLP packaging methods. From the performance specs it looks like superior packaging can be the equivalent of a node shrink. With TSM having its InFO process heavily protected by a substantial patent wall, this should give TSM an advantage for years to come. Any thoughts, comments or opinions on this would be appreciated sinSce this is a new area of study for me. I feel this will play a major part who wins the SOC/MEMs/sensor chips we are going to see penetrate into every area of our lives.
The comment I would make is that the A10 uses this advanced TSMC packaging for both the 2GiB (iPhone7) and 3GiB (iPhone7+) package BUT the A01X does not do so.
The differences between the A10 and A10X (A10X connects to 4GiB of DRAM, mounted next to the SoC, on the PCB), A10X connected to DRAM via 128 bits rather than 64 bits, do not seem to explain this difference.
Obviously A10X has 3 cores (at the same frequency) and twice as much GPU, so it's somewhat larger and runs somewhat hotter, but again the differences do not seem extreme enough to prevent mounting the DRAM on the SoC, with the consequent small improvements in energy (shorter wires and all that).
(The same difference was true, BTW, for at least the A9 and A9X; can't remember A8 vs A8X).
So what does this tell us? The packaging is expensive enough that it's not going to be used except where essential? (Apple can't afford space on the phone PCB, but can on the iPad PCB?)
Or the packaging requires advanced machinery of which there is a limited amount, so A10's go to the front of the queue, but A10X couldn't get a slot?
