TSMC is pushing the boundaries of semiconductor manufacturing with plans to begin trial production of its sub-1nm A10 process technology by 2029, according to recent reports from Wccftech and other industry outlets. Apple, the foundry giant's largest smartphone chip customer, is widely expected to be among the first to adopt the next-generation node, which would power future iPhones and Macs.
The A10 process, which TSMC designates as its sub-1nm node, would target volume manufacturing around 2030, following the typical one-to-two-year gap between trial and mass production. The move extends TSMC's roadmap well beyond its current 2nm generation, which entered mass production in late 2025, and its forthcoming A14 (1.4nm) node slated for 2028.
A14 Paves the Way
Before reaching sub-1nm territory, TSMC is building out its A14 infrastructure. The company is constructing Fab 25 in Taiwan's Central Taiwan Science Park at a cost of roughly $49 billion, with risk production of the 1.4nm process expected by late 2027 and full-scale manufacturing by the second half of 2028. A14 promises a 15 percent performance boost at the same power level and up to a 30 percent reduction in power consumption compared to the N2 node.
Apple is reportedly planning to skip TSMC's A16 (1.6nm) node — where Nvidia is expected to be the lead customer — and jump directly to A14 for its next major chip generation. That leap would give Apple a full node advantage over competitors still using 2nm-class silicon.
The Race to 1nm
TSMC is not alone in targeting the 1nm frontier. Japan's government-backed Rapidus aims for 1nm mass production by 2029, while Samsung has formed a dedicated team for 1nm development with a similar 2029 mass-production target, according to a report from South Korea's SEDaily. Intel is also pursuing its own 1.4nm node for 2028.
However, TSMC's yield advantage remains formidable. Its N2 process is estimated to achieve yields of 65 to 75 percent, compared to roughly 55 percent for Samsung's comparable SF2 node, according to industry estimates cited by XenoSpectrum. TSMC held approximately 64 percent of the global foundry market at the end of 2024.
Physical Limits Ahead
The sub-1nm designation reflects "equivalent scaling" through a combination of advanced transistor architectures, packaging, and power delivery improvements rather than a literal sub-1nm gate length. TSMC has indicated at the International Electron Devices Meeting that the A10 generation aims to integrate 200 billion transistors on a single chip, with chiplet integration pushing toward one trillion transistors per package. High-NA EUV lithography from ASML is expected to enter volume use at this node for the first time.