Taiwan-based semiconductor foundry leader Taiwan Semiconductor Manufacturing Co. (TSMC) has begun volume production of chips using its 2nm-class N2 process, according to information disclosed on the company's official website.
While TSMC did not issue a standalone press release, a statement on its N2 technology page confirms that "TSMC's 2nm (N2) technology has started volume production in the fourth quarter of 2025 as planned," fulfilling the company's previously stated roadmap.
Compared with the N3E node, N2 is designed to deliver a 10% to 15% performance gain at the same power, or a 25% to 30% reduction in power at the same performance, along with a 15% increase in transistor density for mixed designs that include logic, SRAM, and analog circuits. For logic-only designs, density gains can reach up to 20%.
*Chip density published by TSMC reflects 'mixed' chip density consisting of 50% logic, 30% SRAM, and 20% analog.
**At the same speed.
***At the same power.
N2 is TSMC's first process node to adopt gate-all-around nanosheet transistors, a major architectural shift that improves electrostatic control, reduces leakage, and enables further scaling without compromising performance or power efficiency. The node also introduces super-high-performance metal-insulator-metal capacitors in the power delivery network, enhancing power stability and overall energy efficiency.
Speaking during the company's earnings call in October, TSMC Chairman and CEO C.C. Wei said the N2 process was "well on track for volume production later this quarter, with good yield," adding that a faster ramp is expected in 2026, driven by demand from smartphones and high-performance computing, including AI applications.
Industry sources indicate that initial N2 volume production has begun at TSMC's Fab 22 near Kaohsiung in southern Taiwan, rather than at Fab 20 near Hsinchu, which is adjacent to the company's global R&D center where N2 technologies were developed. Fab 20 is expected to enter mass production at a later stage.
TSMC plans to ramp N2 production across new fabs serving both mobile and larger AI and HPC designs, reflecting strong customer interest in the node. Beginning in the second half of 2026, the company also plans to introduce N2P, a performance-enhanced version of N2, and A16, which incorporates backside power delivery technology aimed at advanced AI and HPC processors.
"With our strategy of continuous enhancements, we will introduce N2P as an extension of our N2 family, followed by A16, both scheduled for volume production in the second half of 2026," Wei said.
www.ic-pcb.com
While TSMC did not issue a standalone press release, a statement on its N2 technology page confirms that "TSMC's 2nm (N2) technology has started volume production in the fourth quarter of 2025 as planned," fulfilling the company's previously stated roadmap.
Compared with the N3E node, N2 is designed to deliver a 10% to 15% performance gain at the same power, or a 25% to 30% reduction in power at the same performance, along with a 15% increase in transistor density for mixed designs that include logic, SRAM, and analog circuits. For logic-only designs, density gains can reach up to 20%.
*Chip density published by TSMC reflects 'mixed' chip density consisting of 50% logic, 30% SRAM, and 20% analog.
**At the same speed.
***At the same power.
N2 is TSMC's first process node to adopt gate-all-around nanosheet transistors, a major architectural shift that improves electrostatic control, reduces leakage, and enables further scaling without compromising performance or power efficiency. The node also introduces super-high-performance metal-insulator-metal capacitors in the power delivery network, enhancing power stability and overall energy efficiency.
Speaking during the company's earnings call in October, TSMC Chairman and CEO C.C. Wei said the N2 process was "well on track for volume production later this quarter, with good yield," adding that a faster ramp is expected in 2026, driven by demand from smartphones and high-performance computing, including AI applications.
Industry sources indicate that initial N2 volume production has begun at TSMC's Fab 22 near Kaohsiung in southern Taiwan, rather than at Fab 20 near Hsinchu, which is adjacent to the company's global R&D center where N2 technologies were developed. Fab 20 is expected to enter mass production at a later stage.
TSMC plans to ramp N2 production across new fabs serving both mobile and larger AI and HPC designs, reflecting strong customer interest in the node. Beginning in the second half of 2026, the company also plans to introduce N2P, a performance-enhanced version of N2, and A16, which incorporates backside power delivery technology aimed at advanced AI and HPC processors.
"With our strategy of continuous enhancements, we will introduce N2P as an extension of our N2 family, followed by A16, both scheduled for volume production in the second half of 2026," Wei said.
Tsmc Quietly Begins Volume Production Of 2nm-Class Chips
The world's leading contract chipmaker TSMC has quietly entered volume production of its 2nm-class N2 process in the fourth quarter of 2025, marking a major milestone in advanced logic manufacturing and setting the stage for a broader ramp driven by smartphone and AI-related demand in 2026.
www.ic-pcb.com
