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TSMC Holds 3nm Volume Production and Capacity Expansion Ceremony, Marking a Key Milestone for Advanced Manufacturing

Daniel Nenni

Daniel Nenni

Admin
Staff member
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HSINCHU, Taiwan, R.O.C. – Dec. 29, 2022 - TSMC (TWSE: 2330, NYSE: TSM) today held a 3 nanometer (3nm) Volume Production and Capacity Expansion Ceremony at its Fab 18 new construction site in the Southern Taiwan Science Park (STSP), bringing together suppliers, construction partners, central and local government, the Taiwan Semiconductor Industry Association, and members of academia to witness an important milestone in the Company’s advanced manufacturing.

TSMC has laid a strong foundation for 3nm technology and capacity expansion, with Fab 18 located in the STSP serving as the Company’s GIGAFAB® facility producing 5nm and 3nm process technology. Today, TSMC announced that 3nm technology has successfully entered volume production with good yields, and held a topping ceremony for its Fab 18 Phase 8 facility. TSMC estimates that 3nm technology will create end products with a market value of US$1.5 trillion within five years of volume production.

Phases 1 through 8 of TSMC Fab 18 each have cleanroom area of 58,000 square meters, approximately double the size of a standard logic fab. TSMC’s total investment in Fab 18 will exceed NT$1.86 trillion, creating more than 23,500 construction jobs and over 11,300 high-tech direct job opportunities. In addition to expanding 3nm capacity in Taiwan, TSMC is also building 3nm capacity at its Arizona site.

TSMC also announced that the Company’s global R&D Center in the Hsinchu Science Park will officially open in the second quarter of 2023, to be staffed by 8,000 R&D personnel. TSMC is also making preparations for its 2nm fabs, which will be located in the Hsinchu and Central Taiwan Science Parks, with a total of six phases proceeding as planned.

TSMC Chairman Dr. Mark Liu presided over 3nm Volume Production and Capacity Expansion Ceremony, and notable guests at the event included Vice Premier Shen Jong-chin, Minister of Economic Affairs Wang Mei-hua, Minister of Science and Technology Wu Tsung-tsong, Tainan City Mayor Huang Wei-che, STSP Administration Bureau Director-General Su Chen-kang, Fu Tsu Construction Chairman Cliff Lin, United Integrated Services Chairman Belle Lee, National Cheng Kung University President Dr. Jenny Su, Chang Chun Petrochemical President Chih-Chuan Tsai, Kuang Ming Enterprise Co. Vice Chairman Eric Lin, and Applied Materials Group Vice President Erix Yu, as well as representatives from TSMC’s construction partners, materials and equipment suppliers, the Taiwan Semiconductor Industry Association and academic institutions.

“TSMC is maintaining its technology leadership while investing significantly in Taiwan, continuing to invest and prosper with the environment. This 3nm Volume Production and Capacity Expansion Ceremony demonstrates that we are taking concrete action to develop advanced technology and expand capacity in Taiwan,” TSMC Chairman Dr. Mark Liu said at the ceremony. “We aim to grow together with our upstream and downstream supply chain and develop future talent from design to manufacturing, packaging and testing, equipment, and materials to provide the most competitive advanced process technology and reliable capacity for the world and drive technology innovation in the future.”

TSMC is committed to flourishing with the natural environment through green manufacturing, and all of TSMC’s construction in the STSP follows Taiwan’s EEWH and the U.S. LEED green building certification standards. The facilities will also use water resources from the TSMC STSP Reclaimed Water Plant to gradually reach the company’s target of using 60% reclaimed water by 2030. Once volume production begins, Fab 18 will use 20% renewable energy to eventually reach the sustainability goal of 100% renewable energy and zero emissions by 2050.

TSMC’s 3nm process is the most advanced semiconductor technology in both power, performance, and area (PPA) and in transistor technology, and a full-node advance from the 5nm generation. Compared with the 5nm (N5) process, TSMC’s 3nm process offers up to 1.6X logic density gain and 30-35% power reduction at the same speed, and supports the innovative TSMC FINFLEX™ architecture.

TSMC Spokesperson​

Wendell Huang
Vice President & Chief Financial Officer
Tel:886-3-5055901

TSMC Deputy Spokesperson​

Nina Kao
Public Relations Division
Tel:886-3-5636688 Ext.7125036
 
Daniel Nenni said:
View attachment 1007

HSINCHU, Taiwan, R.O.C. – Dec. 29, 2022 - TSMC (TWSE: 2330, NYSE: TSM) today held a 3 nanometer (3nm) Volume Production and Capacity Expansion Ceremony at its Fab 18 new construction site in the Southern Taiwan Science Park (STSP), bringing together suppliers, construction partners, central and local government, the Taiwan Semiconductor Industry Association, and members of academia to witness an important milestone in the Company’s advanced manufacturing.

TSMC has laid a strong foundation for 3nm technology and capacity expansion, with Fab 18 located in the STSP serving as the Company’s GIGAFAB® facility producing 5nm and 3nm process technology. Today, TSMC announced that 3nm technology has successfully entered volume production with good yields, and held a topping ceremony for its Fab 18 Phase 8 facility. TSMC estimates that 3nm technology will create end products with a market value of US$1.5 trillion within five years of volume production.

Phases 1 through 8 of TSMC Fab 18 each have cleanroom area of 58,000 square meters, approximately double the size of a standard logic fab. TSMC’s total investment in Fab 18 will exceed NT$1.86 trillion, creating more than 23,500 construction jobs and over 11,300 high-tech direct job opportunities. In addition to expanding 3nm capacity in Taiwan, TSMC is also building 3nm capacity at its Arizona site.

TSMC also announced that the Company’s global R&D Center in the Hsinchu Science Park will officially open in the second quarter of 2023, to be staffed by 8,000 R&D personnel. TSMC is also making preparations for its 2nm fabs, which will be located in the Hsinchu and Central Taiwan Science Parks, with a total of six phases proceeding as planned.

TSMC Chairman Dr. Mark Liu presided over 3nm Volume Production and Capacity Expansion Ceremony, and notable guests at the event included Vice Premier Shen Jong-chin, Minister of Economic Affairs Wang Mei-hua, Minister of Science and Technology Wu Tsung-tsong, Tainan City Mayor Huang Wei-che, STSP Administration Bureau Director-General Su Chen-kang, Fu Tsu Construction Chairman Cliff Lin, United Integrated Services Chairman Belle Lee, National Cheng Kung University President Dr. Jenny Su, Chang Chun Petrochemical President Chih-Chuan Tsai, Kuang Ming Enterprise Co. Vice Chairman Eric Lin, and Applied Materials Group Vice President Erix Yu, as well as representatives from TSMC’s construction partners, materials and equipment suppliers, the Taiwan Semiconductor Industry Association and academic institutions.

“TSMC is maintaining its technology leadership while investing significantly in Taiwan, continuing to invest and prosper with the environment. This 3nm Volume Production and Capacity Expansion Ceremony demonstrates that we are taking concrete action to develop advanced technology and expand capacity in Taiwan,” TSMC Chairman Dr. Mark Liu said at the ceremony. “We aim to grow together with our upstream and downstream supply chain and develop future talent from design to manufacturing, packaging and testing, equipment, and materials to provide the most competitive advanced process technology and reliable capacity for the world and drive technology innovation in the future.”

TSMC is committed to flourishing with the natural environment through green manufacturing, and all of TSMC’s construction in the STSP follows Taiwan’s EEWH and the U.S. LEED green building certification standards. The facilities will also use water resources from the TSMC STSP Reclaimed Water Plant to gradually reach the company’s target of using 60% reclaimed water by 2030. Once volume production begins, Fab 18 will use 20% renewable energy to eventually reach the sustainability goal of 100% renewable energy and zero emissions by 2050.

TSMC’s 3nm process is the most advanced semiconductor technology in both power, performance, and area (PPA) and in transistor technology, and a full-node advance from the 5nm generation. Compared with the 5nm (N5) process, TSMC’s 3nm process offers up to 1.6X logic density gain and 30-35% power reduction at the same speed, and supports the innovative TSMC FINFLEX™ architecture.

TSMC Spokesperson​

Wendell Huang
Vice President & Chief Financial Officer
Tel:886-3-5055901

TSMC Deputy Spokesperson​

Nina Kao
Public Relations Division
Tel:886-3-5636688 Ext.7125036
Click to expand...
The scale of TSMC’s expansion is unreal. I can’t wrap my head around it.
 
Is there anything actually more complex (man-made) on this Earth than what's required to manufacture chips on this advanced of a process?
 
Is Samsung building anywhere near as rapid as this? I guess there aren’t many lining up for their 3nm GAA.
 
This ceremony highlights TSMC ongoing commitment to build out new capa in Taiwan, as well as the US. There are 4 sites in Taiwan and 1 in the US, so the ratio is 80/20 in favor in Taiwan. That’s one message, I think.

Robert MaIre wrote about Micron’s quarter and had a negative outlook. Semi stocks are down, including TSMC (time to buy?) This annoucement may also keep focus on the future in the hope of increasing the stock price.

Announcing expansion, rather than layoffs, is also a message.
 
Last edited:
benb said:
Robert MaIre wrote about Micron’s quarter and had a negative outlook. Semi stocks are down, including TSMC (time to buy?)
Click to expand...
If Kevin McCarthy is elected to be US Speaker of the House next year, he has committed to visiting Taiwan. China will likely respond like they did with Pelosi's trip, TSM stock might sink again to a new low, and that's when I'll probably buy to shore up my current position.
 
blueone said:
If Kevin McCarthy is elected to be US Speaker of the House next year, he has committed to visiting Taiwan. China will likely respond like they did with Pelosi's trip, TSM stock might sink again to a new low, and that's when I'll probably buy to shore up my current position.
Click to expand...
I don’t get how people sell off in those situations. If anything U.S leadership visiting makes conflict less likely as it demonstrates we are more then likely not going to leave Taiwan out to dry. As evil as the CCP is they aren’t going to 1v1 the U.S.
 
benb said:
This ceremony highlights TSMC ongoing commitment to build out new capa in Taiwan, as well as the US. There are 4 sites in Taiwan and 1 in the US, so the ratio is 80/20 in favor in Taiwan. That’s one message, I think.
Click to expand...
Not even close. Each of those four 12in sites are WAAAAAAY higher capacity than the AZ fab is or will ever be able to expand to. Don’t get me wrong AZ is great and a monumental step as TSMC dips its toe in the distributed production network pool. But we must also not delude ourselves into thinking the supply chain is now “resilient” and that “we’re done here”. TSMC is still, and barring a horrible disaster, will always be a Taiwanese company with little outposts spread throughout the wider world. All of the companies that were at the AZ fab tool-in ceremony could probably fill it just with their own orders. To say nothing of all of them combined plus chips for the US government or future automaker orders for advanced finFETs.
 
nghanayem said:
Not even close. Each of those four 12in sites are WAAAAAAY higher capacity than the AZ fab is or will ever be able to expand to. Don’t get me wrong AZ is great and a monumental step as TSMC dips its toe in the distributed production network pool. But we must also not delude ourselves into thinking the supply chain is now “resilient” and that “we’re done here”. TSMC is still, and barring a horrible disaster, will always be a Taiwanese company with little outposts spread throughout the wider world. All of the companies that were at the AZ fab tool-in ceremony could probably fill it just with their own orders. To say nothing of all of them combined plus chips for the US government or future automaker orders for advanced finFETs.
Click to expand...
Anyone know how TSMC 3nm is yielding when compared to Samsung 3GAA? Also how are things going over at Intel 4,3 etc
 
Mooredaddy said:
Anyone know how TSMC 3nm is yielding when compared to Samsung 3GAA? Also how are things going over at Intel 4,3 etc
Click to expand...
Better. 3GAE must be pixie dust right now considering 4LPE is in a similar camp and that is just a pimped out 7LPP, and i4 hasn't been ramping for as long as N3 so it would stand to reason that it is less far along the track. Also as Dan has pointed out the "half-baked" nature of i4 doesn't really invite apples to apples comparisons to N3 (not to say you can't, but it always has to be done with the caveat that it isn't yet the full process). Intel 3 should be a piece of cake from the defect density side, a bit harder on the PDK front, and the performance uplift seems very aggressive for a node that doesn't seem to be shrinking pitches (after all we are talking something bigger than 10nm "superfin" and even slightly bigger the uplift from N5 to N3). I general though I dislike the term yield when comparing processes, since it is too design dependent. Yield can be parametric fails (like what is reported for 4LPE) or fails from defects (like 10nm or what is likely going on with N3) that get worse the larger the die gets.
 
Last edited:
hist78 said:
Here is a rumor about TSMC's N3 yield. It is between 60% and 80%.

Analysts Estimate TSMC's 3nm Yields Between 60% and 80%

There are thousands of ways to improve yields.
www.tomshardware.com www.tomshardware.com
Click to expand...
I wouldn't put much stock in that. How big is the die? How closely was the PDKs being followed? Are they pushing the density limits? Is this "yield" wafers that reach end of line, functional die, or the percent of die that are sellable? Does their design do stuff that isn't well defined by the PDK? ect ect. Way too many variables to just blanket say yields are between x and y. There is a big difference between Apple with a well designed tiny die with crazy good yields and a giant died NVIDIA product where the engineers tried to break every design rule possible (and then proceed to blame TSMC or Samsung for poor yields); and both of these things can happen on the same node at the same time.
 
nghanayem said:
Better. 3GAE must be pixie dust right now considering 4LPE is in a similar camp and that is just a pimped out 7LPP, and i4 hasn't been ramping for as long as N3 so it would stand to reason that it is less far along the track. Also as Dan has pointed out the "half-baked" nature of i4 doesn't really invite apples to apples comparisons to N3 (not to say you can't, but it always has to be done with the caveat that it isn't yet the full process). Intel 3 should be a piece of cake from the defect density side, a bit harder on the PDK front, and the performance uplift seems very aggressive for a node that doesn't seem to be shrinking pitches (after all we are talking something bigger than 10nm "superfin" and even slightly bigger the uplift from N5 to N3). I general though I dislike the term yield when comparing processes, since it is too design dependent. Yield can be parametric fails (like what is reported for 4LPE) or fails from defects (like 10nm or what is likely going on with N3) that get worse the larger the die gets.
Click to expand...
I wish we got more clarity directly from the manufacturers on how processes are yielding. Just so much guess work to figure out what is really going on inside these black boxes that are semi fabs.
 
Mooredaddy said:
I wish we got more clarity directly from the manufacturers on how processes are yielding. Just so much guess work to figure out what is really going on inside these black boxes that are semi fabs.
Click to expand...
While not exactly a cheap solution you can always ask for PDKs and the like. Or if you are feeling like a highroller you can send out a testchip. It'll give you far more information than somebody telling you "looks healthy" or "yields are bad" since you would know exactly how it performs for your chip.
 
I agree with nghanayem, yields are misunderstood, totally.

From my perspective, yields are an output, a target we seek to improve, within economic constraints, and then seek to maintain. But it varies, a lot.

Fabs live in fear of excursions. This is when a bunch of wafers have to be scrapped due to some quality issue that wasn’t detected, before it reaches the customer. Part of the reason for the secrecy around yields is excursions would be obvious, a sudden dip in yields. For some customers and some products an excursion would limit delivery and affect their price negotiations, and so to protect customers, yields are secret.
 
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